162d95512SEric Auger /* 262d95512SEric Auger * VFIO AMD XGBE device 362d95512SEric Auger * 462d95512SEric Auger * Copyright Linaro Limited, 2015 562d95512SEric Auger * 662d95512SEric Auger * Authors: 762d95512SEric Auger * Eric Auger <eric.auger@linaro.org> 862d95512SEric Auger * 962d95512SEric Auger * This work is licensed under the terms of the GNU GPL, version 2. See 1062d95512SEric Auger * the COPYING file in the top-level directory. 1162d95512SEric Auger * 1262d95512SEric Auger */ 1362d95512SEric Auger 1462d95512SEric Auger #ifndef HW_VFIO_VFIO_AMD_XGBE_H 1562d95512SEric Auger #define HW_VFIO_VFIO_AMD_XGBE_H 1662d95512SEric Auger 1762d95512SEric Auger #include "hw/vfio/vfio-platform.h" 18db1015e9SEduardo Habkost #include "qom/object.h" 1962d95512SEric Auger 2062d95512SEric Auger #define TYPE_VFIO_AMD_XGBE "vfio-amd-xgbe" 2162d95512SEric Auger 2262d95512SEric Auger /** 2362d95512SEric Auger * This device exposes: 2462d95512SEric Auger * - 5 MMIO regions: MAC, PCS, SerDes Rx/Tx regs, 2562d95512SEric Auger SerDes Integration Registers 1/2 & 2/2 2662d95512SEric Auger * - 2 level sensitive IRQs and optional DMA channel IRQs 2762d95512SEric Auger */ 2862d95512SEric Auger struct VFIOAmdXgbeDevice { 2962d95512SEric Auger VFIOPlatformDevice vdev; 3062d95512SEric Auger }; 3162d95512SEric Auger 3262d95512SEric Auger typedef struct VFIOAmdXgbeDevice VFIOAmdXgbeDevice; 3362d95512SEric Auger 3462d95512SEric Auger struct VFIOAmdXgbeDeviceClass { 3562d95512SEric Auger /*< private >*/ 3662d95512SEric Auger VFIOPlatformDeviceClass parent_class; 3762d95512SEric Auger /*< public >*/ 3862d95512SEric Auger DeviceRealize parent_realize; 3962d95512SEric Auger }; 4062d95512SEric Auger 4162d95512SEric Auger typedef struct VFIOAmdXgbeDeviceClass VFIOAmdXgbeDeviceClass; 4262d95512SEric Auger 43*8110fa1dSEduardo Habkost DECLARE_OBJ_CHECKERS(VFIOAmdXgbeDevice, VFIOAmdXgbeDeviceClass, 44*8110fa1dSEduardo Habkost VFIO_AMD_XGBE_DEVICE, TYPE_VFIO_AMD_XGBE) 4562d95512SEric Auger 4662d95512SEric Auger #endif 47