xref: /openbmc/u-boot/doc/device-tree-bindings/gpio/nvidia,tegra20-gpio.txt (revision e1cc4d31f889428a4ca73120951389c756404184)
1*5cfc662cSSimon GlassNVIDIA Tegra GPIO controller
2*5cfc662cSSimon Glass
3*5cfc662cSSimon GlassRequired properties:
4*5cfc662cSSimon Glass- compatible : "nvidia,tegra<chip>-gpio"
5*5cfc662cSSimon Glass- reg : Physical base address and length of the controller's registers.
6*5cfc662cSSimon Glass- interrupts : The interrupt outputs from the controller. For Tegra20,
7*5cfc662cSSimon Glass  there should be 7 interrupts specified, and for Tegra30, there should
8*5cfc662cSSimon Glass  be 8 interrupts specified.
9*5cfc662cSSimon Glass- #gpio-cells : Should be two. The first cell is the pin number and the
10*5cfc662cSSimon Glass  second cell is used to specify optional parameters:
11*5cfc662cSSimon Glass  - bit 0 specifies polarity (0 for normal, 1 for inverted)
12*5cfc662cSSimon Glass- gpio-controller : Marks the device node as a GPIO controller.
13*5cfc662cSSimon Glass- #interrupt-cells : Should be 2.
14*5cfc662cSSimon Glass  The first cell is the GPIO number.
15*5cfc662cSSimon Glass  The second cell is used to specify flags:
16*5cfc662cSSimon Glass    bits[3:0] trigger type and level flags:
17*5cfc662cSSimon Glass      1 = low-to-high edge triggered.
18*5cfc662cSSimon Glass      2 = high-to-low edge triggered.
19*5cfc662cSSimon Glass      4 = active high level-sensitive.
20*5cfc662cSSimon Glass      8 = active low level-sensitive.
21*5cfc662cSSimon Glass      Valid combinations are 1, 2, 3, 4, 8.
22*5cfc662cSSimon Glass- interrupt-controller : Marks the device node as an interrupt controller.
23*5cfc662cSSimon Glass
24*5cfc662cSSimon GlassExample:
25*5cfc662cSSimon Glass
26*5cfc662cSSimon Glassgpio: gpio@6000d000 {
27*5cfc662cSSimon Glass	compatible = "nvidia,tegra20-gpio";
28*5cfc662cSSimon Glass	reg = < 0x6000d000 0x1000 >;
29*5cfc662cSSimon Glass	interrupts = < 0 32 0x04
30*5cfc662cSSimon Glass		       0 33 0x04
31*5cfc662cSSimon Glass		       0 34 0x04
32*5cfc662cSSimon Glass		       0 35 0x04
33*5cfc662cSSimon Glass		       0 55 0x04
34*5cfc662cSSimon Glass		       0 87 0x04
35*5cfc662cSSimon Glass		       0 89 0x04 >;
36*5cfc662cSSimon Glass	#gpio-cells = <2>;
37*5cfc662cSSimon Glass	gpio-controller;
38*5cfc662cSSimon Glass	#interrupt-cells = <2>;
39*5cfc662cSSimon Glass	interrupt-controller;
40*5cfc662cSSimon Glass};
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