1*d839e821SVladimir Zapolskiy* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers 2eb3fcf00SRob Herring 3eb3fcf00SRob HerringRequired properties: 4*d839e821SVladimir Zapolskiy- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic". 5*d839e821SVladimir Zapolskiy- reg: should contain IC registers location and length. 6*d839e821SVladimir Zapolskiy- interrupt-controller: identifies the node as an interrupt controller. 7*d839e821SVladimir Zapolskiy- #interrupt-cells: the number of cells to define an interrupt, should be 2. 8*d839e821SVladimir Zapolskiy The first cell is the IRQ number, the second cell is used to specify 9*d839e821SVladimir Zapolskiy one of the supported IRQ types: 10*d839e821SVladimir Zapolskiy IRQ_TYPE_EDGE_RISING = low-to-high edge triggered, 11*d839e821SVladimir Zapolskiy IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered, 12*d839e821SVladimir Zapolskiy IRQ_TYPE_LEVEL_HIGH = active high level-sensitive, 13*d839e821SVladimir Zapolskiy IRQ_TYPE_LEVEL_LOW = active low level-sensitive. 14*d839e821SVladimir Zapolskiy Reset value is IRQ_TYPE_LEVEL_LOW. 15*d839e821SVladimir Zapolskiy 16*d839e821SVladimir ZapolskiyOptional properties: 17*d839e821SVladimir Zapolskiy- interrupts: empty for MIC interrupt controller, cascaded MIC 18*d839e821SVladimir Zapolskiy hardware interrupts for SIC1 and SIC2 19eb3fcf00SRob Herring 20eb3fcf00SRob HerringExamples: 21*d839e821SVladimir Zapolskiy 22*d839e821SVladimir Zapolskiy /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */ 23eb3fcf00SRob Herring mic: interrupt-controller@40008000 { 24eb3fcf00SRob Herring compatible = "nxp,lpc3220-mic"; 25*d839e821SVladimir Zapolskiy reg = <0x40008000 0x4000>; 26eb3fcf00SRob Herring interrupt-controller; 27eb3fcf00SRob Herring #interrupt-cells = <2>; 28eb3fcf00SRob Herring }; 29eb3fcf00SRob Herring 30*d839e821SVladimir Zapolskiy sic1: interrupt-controller@4000c000 { 31*d839e821SVladimir Zapolskiy compatible = "nxp,lpc3220-sic"; 32*d839e821SVladimir Zapolskiy reg = <0x4000c000 0x4000>; 33*d839e821SVladimir Zapolskiy interrupt-controller; 34*d839e821SVladimir Zapolskiy #interrupt-cells = <2>; 35*d839e821SVladimir Zapolskiy 36*d839e821SVladimir Zapolskiy interrupt-parent = <&mic>; 37*d839e821SVladimir Zapolskiy interrupts = <0 IRQ_TYPE_LEVEL_LOW>, 38*d839e821SVladimir Zapolskiy <30 IRQ_TYPE_LEVEL_LOW>; 39*d839e821SVladimir Zapolskiy }; 40*d839e821SVladimir Zapolskiy 41*d839e821SVladimir Zapolskiy sic2: interrupt-controller@40010000 { 42*d839e821SVladimir Zapolskiy compatible = "nxp,lpc3220-sic"; 43*d839e821SVladimir Zapolskiy reg = <0x40010000 0x4000>; 44*d839e821SVladimir Zapolskiy interrupt-controller; 45*d839e821SVladimir Zapolskiy #interrupt-cells = <2>; 46*d839e821SVladimir Zapolskiy 47*d839e821SVladimir Zapolskiy interrupt-parent = <&mic>; 48*d839e821SVladimir Zapolskiy interrupts = <1 IRQ_TYPE_LEVEL_LOW>, 49*d839e821SVladimir Zapolskiy <31 IRQ_TYPE_LEVEL_LOW>; 50*d839e821SVladimir Zapolskiy }; 51*d839e821SVladimir Zapolskiy 52*d839e821SVladimir Zapolskiy /* ADC */ 53eb3fcf00SRob Herring adc@40048000 { 54eb3fcf00SRob Herring compatible = "nxp,lpc3220-adc"; 55eb3fcf00SRob Herring reg = <0x40048000 0x1000>; 56*d839e821SVladimir Zapolskiy interrupt-parent = <&sic1>; 57*d839e821SVladimir Zapolskiy interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 58eb3fcf00SRob Herring }; 59