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123

/openbmc/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dvsc8211.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
53 VSC_INTR_DESCRAMBL = 1 << 7, /* descrambler lock-lost */
60 VSC_INTR_ENABLE = 1 << 15, /* interrupt enable */
133 unsigned int bmcr, status, lpa, adv; in vsc8211_get_link_status() local
134 int err, sp = -1, dplx = -1, pause = 0; in vsc8211_get_link_status()
144 * BMSR_LSTATUS is latch-low, so if it is 0 we need to read it in vsc8211_get_link_status()
179 &lpa); in vsc8211_get_link_status()
186 if (lpa & adv & ADVERTISE_PAUSE_CAP) in vsc8211_get_link_status()
[all …]
/openbmc/u-boot/drivers/net/phy/
H A Dmeson-gxl.c1 // SPDX-License-Identifier: GPL-2.0+
18 * - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that
21 * - Late failures: MII_LPA is filled with a value which seems to make sense
23 * can detect this using a magic bit in the WOL bank (reg 12 - bit 12).
34 int ret, wol, lpa, exp; in meson_gxl_startup() local
41 if (phydev->autoneg == AUTONEG_ENABLE) { in meson_gxl_startup()
66 lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); in meson_gxl_startup()
67 if (lpa < 0) in meson_gxl_startup()
68 return lpa; in meson_gxl_startup()
75 ((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) { in meson_gxl_startup()
[all …]
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0+
27 * genphy_config_advert - sanitize and advertise auto-negotiation parameters
42 phydev->advertising &= phydev->supported; in genphy_config_advert()
43 advertise = phydev->advertising; in genphy_config_advert()
83 /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all in genphy_config_advert()
99 if (phydev->supported & (SUPPORTED_1000baseT_Half | in genphy_config_advert()
118 * genphy_setup_forced - configures/forces speed/duplex from @phydev
129 phydev->pause = 0; in genphy_setup_forced()
130 phydev->asym_pause = 0; in genphy_setup_forced()
132 if (phydev->speed == SPEED_1000) in genphy_setup_forced()
[all …]
/openbmc/linux/drivers/net/phy/
H A Dlxt.c1 // SPDX-License-Identifier: GPL-2.0+
34 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
44 /* ------------------------------------------------------------------------- */
48 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
83 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in lxt970_config_intr()
147 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in lxt971_config_intr()
206 } while (status >= 0 && retry-- && status == control); in lxt973a2_update_link()
212 phydev->link = 0; in lxt973a2_update_link()
214 phydev->link = 1; in lxt973a2_update_link()
223 int lpa; in lxt973a2_read_status() local
[all …]
H A Dmeson-gxl.c1 // SPDX-License-Identifier: GPL-2.0+
45 /* Enable Analog and DSP register Bank access by in meson_gxl_open_banks()
117 /* Enable fractional PLL */ in meson_gxl_config_init()
138 * - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that
141 * - Late failures: MII_LPA is filled with a value which seems to make sense
143 * can detect this using a magic bit in the WOL bank (reg 12 - bit 12).
153 int ret, wol, lpa, exp; in meson_gxl_read_status() local
155 if (phydev->autoneg == AUTONEG_ENABLE) { in meson_gxl_read_status()
167 lpa = phy_read(phydev, MII_LPA); in meson_gxl_read_status()
168 if (lpa < 0) in meson_gxl_read_status()
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H A Dmotorcomm.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: Frank <Frank.Sae@motor-comm.com>
22 * ------------------------------------------------------------
26 * ------------------------------------------------------------
28 * ------------------------------------------------------------
39 * 2b11 Enable automatic crossover for all modes *default*
67 /* Interrupt enable Register */
104 /* FIBER Auto-Negotiation link partner ability */
125 /* TX Gig-E Delay is bits 7:4, default 0x5
126 * TX Fast-E Delay is bits 15:12, default 0xf
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H A Dmarvell.c1 // SPDX-License-Identifier: GPL-2.0+
142 /* Copper Specific Interrupt Enable Register */
144 /* WOL Event Interrupt Enable */
188 /* RGMII to 1000BASE-X */
190 /* RGMII to 100BASE-FX */
347 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in marvell_config_intr()
411 err = marvell_set_polarity(phydev, phydev->mdix_ctrl); in marvell_config_aneg()
426 if (phydev->autoneg != AUTONEG_ENABLE || changed) { in marvell_config_aneg()
476 * marvell,reg-init property stored in the of_node for the phydev.
478 * marvell,reg-init = <reg-page reg mask value>,...;
[all …]
H A Dphy_device.c1 // SPDX-License-Identifier: GPL-2.0+
32 #include <linux/pse-pd/pse.h>
240 put_device(&phydev->mdio.dev); in phy_device_free()
254 fwnode_handle_put(dev->fwnode); in phy_device_release()
273 struct device_driver *drv = phydev->mdio.dev.driver; in mdio_bus_phy_may_suspend()
275 struct net_device *netdev = phydev->attached_dev; in mdio_bus_phy_may_suspend()
277 if (!drv || !phydrv->suspend) in mdio_bus_phy_may_suspend()
281 * suspended as part of a prior call to phy_disconnect() -> in mdio_bus_phy_may_suspend()
282 * phy_detach() -> phy_suspend() because the parent netdev might be the in mdio_bus_phy_may_suspend()
288 if (netdev->wol_enabled) in mdio_bus_phy_may_suspend()
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H A Dphylink.c1 // SPDX-License-Identifier: GPL-2.0
4 * technologies such as SFP cages where the PHY is hot-pluggable.
44 * struct phylink - internal data type for phylink
60 u8 link_port; /* The current non-phy ethtool port */
93 if ((pl)->config->type == PHYLINK_NETDEV) \
94 netdev_printk(level, (pl)->netdev, fmt, ##__VA_ARGS__); \
95 else if ((pl)->config->type == PHYLINK_DEV) \
96 dev_printk(level, (pl)->dev, fmt, ##__VA_ARGS__); \
108 if ((pl)->config->type == PHYLINK_NETDEV) \
109 netdev_dbg((pl)->netdev, fmt, ##__VA_ARGS__); \
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,rpmsg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
18 Cortex-A and Cortex-M.
21 - $ref: sound-card-common.yaml#
26 - fsl,imx7ulp-rpmsg-audio
27 - fsl,imx8mn-rpmsg-audio
28 - fsl,imx8mm-rpmsg-audio
29 - fsl,imx8mp-rpmsg-audio
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/openbmc/u-boot/drivers/net/
H A Dbcm6368-eth.c1 // SPDX-License-Identifier: GPL-2.0+
19 #define ETH_PORT_STR "brcm,enetsw-port"
150 writel_be(0, priv->base + MII_SC_REG); in bcm6368_mdio_read()
159 writel_be(val, priv->base + MII_SC_REG); in bcm6368_mdio_read()
162 return readw_be(priv->base + MII_DAT_REG); in bcm6368_mdio_read()
170 writel_be(0, priv->base + MII_SC_REG); in bcm6368_mdio_write()
181 writel_be(val, priv->base + MII_SC_REG); in bcm6368_mdio_write()
191 return dma_prepare_rcv_buf(&priv->rx_dma, packet, len); in bcm6368_eth_free_pkt()
198 return dma_receive(&priv->rx_dma, (void**)packetp, NULL); in bcm6368_eth_recv()
207 memset(packet + length, 0, ETH_ZLEN - length); in bcm6368_eth_send()
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H A Ddnet.c43 writel(reg, &dnet->regs->MACREG_ADDR); in dnet_readw_mac()
50 data_read = readl(&dnet->regs->MACREG_DATA); in dnet_readw_mac()
60 writel(val, &dnet->regs->MACREG_DATA); in dnet_writew_mac()
63 writel(reg | DNET_INTERNAL_WRITE, &dnet->regs->MACREG_ADDR); in dnet_writew_mac()
74 debug(DRIVERNAME "dnet_mdio_write %02x:%02x <- %04x\n", in dnet_mdio_write()
75 dnet->phy_addr, reg, value); in dnet_mdio_write()
88 tmp |= (dnet->phy_addr << 8); in dnet_mdio_write()
114 value = (dnet->phy_addr << 8); in dnet_mdio_read()
127 debug(DRIVERNAME "dnet_mdio_read %02x:%02x <- %04x\n", in dnet_mdio_read()
128 dnet->phy_addr, reg, value); in dnet_mdio_read()
[all …]
H A Dmacb.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2005-2006 Atmel Corporation
10 * The u-boot networking stack is a little weird. It seems like the
15 * The MACB receives packets into 128-byte receive buffers, so the
20 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
26 * 32-byte packet "alignment" (which really should be called
40 #include <asm/dma-mapping.h>
178 | MACB_BF(PHYA, macb->phy_addr) in macb_mdio_write()
205 | MACB_BF(PHYA, macb->phy_addr) in macb_mdio_read()
234 struct udevice *dev = eth_get_dev_by_name(bus->name); in macb_miiphy_read()
[all …]
H A Dat91_emac.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Jens Scharsig (esw@bus-elektronik.de)
34 /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
91 /* Mac CTRL reg set for MDIO enable */ in at91emac_EnableMDIO()
92 writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl); in at91emac_EnableMDIO()
98 writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl); in at91emac_DisableMDIO()
110 &at91mac->man); in at91emac_read()
113 netstat = readl(&at91mac->sr); in at91emac_read()
117 *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK; in at91emac_read()
139 &at91mac->man); in at91emac_write()
[all …]
/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dpcs-6352.c1 // SPDX-License-Identifier: GPL-2.0-or-later
43 mutex_lock(&mpcs->mdio.bus->mdio_lock); in marvell_c22_pcs_set_fiber_page()
45 err = __mdiodev_read(&mpcs->mdio, MII_MARVELL_PHY_PAGE); in marvell_c22_pcs_set_fiber_page()
47 dev_err(mpcs->mdio.dev.parent, in marvell_c22_pcs_set_fiber_page()
49 mpcs->name, ERR_PTR(err)); in marvell_c22_pcs_set_fiber_page()
55 err = __mdiodev_write(&mpcs->mdio, MII_MARVELL_PHY_PAGE, in marvell_c22_pcs_set_fiber_page()
58 dev_err(mpcs->mdio.dev.parent, in marvell_c22_pcs_set_fiber_page()
60 mpcs->name, ERR_PTR(err)); in marvell_c22_pcs_set_fiber_page()
73 err = __mdiodev_write(&mpcs->mdio, MII_MARVELL_PHY_PAGE, in marvell_c22_pcs_restore_page()
76 dev_err(mpcs->mdio.dev.parent, in marvell_c22_pcs_restore_page()
[all …]
H A Dpcs-639x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
35 err = mdiodev_c45_read(&mpcs->mdio, MDIO_MMD_PHYXS, regnum); in mv88e639x_read()
46 return mdiodev_c45_write(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, val); in mv88e639x_write()
52 return mdiodev_c45_modify(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, mask, in mv88e639x_modify()
59 return mdiodev_c45_modify_changed(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, in mv88e639x_modify_changed()
73 mpcs->mdio.dev.parent = dev; in mv88e639x_pcs_alloc()
74 mpcs->mdio.bus = bus; in mv88e639x_pcs_alloc()
75 mpcs->mdio.addr = addr; in mv88e639x_pcs_alloc()
77 snprintf(mpcs->name, sizeof(mpcs->name), in mv88e639x_pcs_alloc()
78 "mv88e6xxx-%s-serdes-%d", dev_name(dev), port); in mv88e639x_pcs_alloc()
[all …]
/openbmc/linux/drivers/net/pcs/
H A Dpcs-xpcs.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/pcs/pcs-xpcs.h>
14 #include "pcs-xpcs.h"
167 const struct xpcs_compat *compat = &id->compat[i]; in xpcs_find_compat()
169 for (j = 0; j < compat->num_interfaces; j++) in xpcs_find_compat()
170 if (compat->interface[j] == interface) in xpcs_find_compat()
181 compat = xpcs_find_compat(xpcs->id, interface); in xpcs_get_an_mode()
183 return -ENODEV; in xpcs_get_an_mode()
185 return compat->an_mode; in xpcs_get_an_mode()
194 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) in __xpcs_linkmode_supported()
[all …]
/openbmc/linux/arch/parisc/include/asm/
H A Dspecial_insns.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #define lpa(va) ({ \ macro
35 #define CR_EIEM 15 /* External Interrupt Enable Mask */
/openbmc/u-boot/include/linux/
H A Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
20 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
21 #define MII_STAT1000 0x0a /* 1000BASE-T status */
27 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
44 #define BMCR_PDOWN 0x0800 /* Enable low power state */
45 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
52 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
55 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
57 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
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/openbmc/linux/drivers/net/ethernet/dec/tulip/
H A Dmedia.c5 Written/copyright 1994-2001 by Donald Becker.
21 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
25 /* Read and write the MII registers using software-generated serial
41 Read and write the MII registers using software-generated serial
43 See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management functions")
53 void __iomem *ioaddr = tp->base_addr; in tulip_mdio_read()
60 if (tp->chip_id == COMET && phy_id == 30) { in tulip_mdio_read()
66 spin_lock_irqsave(&tp->mii_lock, flags); in tulip_mdio_read()
67 if (tp->chip_id == LC82C168) { in tulip_mdio_read()
71 for (i = 1000; i >= 0; --i) { in tulip_mdio_read()
[all …]
/openbmc/linux/drivers/net/ethernet/sfc/falcon/
H A Dtenxpress.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2007-2011 Solarflare Communications Inc.
150 /* Enable 312.5 MHz clock */ in tenxpress_init()
170 return -ENOMEM; in tenxpress_phy_probe()
171 efx->phy_data = phy_data; in tenxpress_phy_probe()
172 phy_data->phy_mode = efx->phy_mode; in tenxpress_phy_probe()
174 efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS; in tenxpress_phy_probe()
175 efx->mdio.mode_support = MDIO_SUPPORTS_C45; in tenxpress_phy_probe()
177 efx->loopback_modes = SFX7101_LOOPBACKS | FALCON_XMAC_LOOPBACKS; in tenxpress_phy_probe()
179 efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg | in tenxpress_phy_probe()
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_pcs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
25 #define GMAC_AN_CTRL_RAN BIT(9) /* Restart Auto-Negotiation */
26 #define GMAC_AN_CTRL_ANE BIT(12) /* Auto-Negotiation Enable */
27 #define GMAC_AN_CTRL_ELE BIT(14) /* External Loopback Enable */
28 #define GMAC_AN_CTRL_ECD BIT(16) /* Enable Comma Detect */
34 #define GMAC_AN_STATUS_ANA BIT(3) /* Auto-Negotiation Ability */
35 #define GMAC_AN_STATUS_ANC BIT(5) /* Auto-Negotiation Complete */
38 /* ADV and LPA defines */
48 * dwmac_pcs_isr - TBI, RTBI, or SGMII PHY ISR
53 * Description: it is the ISR for PCS events: Auto-Negotiation Completed and
[all …]
/openbmc/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_port_common.c1 // SPDX-License-Identifier: GPL-2.0-only
23 BUILD_BUG_ON(MC_CMD_GET_PHY_CFG_OUT_NAME_LEN != sizeof(cfg->name)); in efx_mcdi_get_phy_cfg()
31 rc = -EIO; in efx_mcdi_get_phy_cfg()
35 cfg->flags = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_FLAGS); in efx_mcdi_get_phy_cfg()
36 cfg->type = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_TYPE); in efx_mcdi_get_phy_cfg()
37 cfg->supported_cap = in efx_mcdi_get_phy_cfg()
39 cfg->channel = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_CHANNEL); in efx_mcdi_get_phy_cfg()
40 cfg->port = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_PRT); in efx_mcdi_get_phy_cfg()
41 cfg->stats_mask = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_STATS_MASK); in efx_mcdi_get_phy_cfg()
42 memcpy(cfg->name, MCDI_PTR(outbuf, GET_PHY_CFG_OUT_NAME), in efx_mcdi_get_phy_cfg()
[all …]
/openbmc/linux/drivers/net/
H A Dsungem_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * (c) 2002-2007, Benjamin Herrenscmidt (benh@kernel.crashing.org)
10 * - Add support for PHYs that provide an IRQ line
11 * - Eventually moved the entire polling state machine in
14 * - On LXT971 & BCM5201, Apple uses some chip specific regs
17 * - Apple has some additional power management code for some
49 return phy->mdio_read(phy->dev, id, reg); in __sungem_phy_read()
54 phy->mdio_write(phy->dev, id, reg, val); in __sungem_phy_write()
59 return phy->mdio_read(phy->dev, phy->mii_id, reg); in sungem_phy_read()
64 phy->mdio_write(phy->dev, phy->mii_id, reg, val); in sungem_phy_write()
[all …]
/openbmc/linux/drivers/net/ethernet/sfc/
H A Dmcdi_port_common.c1 // SPDX-License-Identifier: GPL-2.0-only
22 BUILD_BUG_ON(MC_CMD_GET_PHY_CFG_OUT_NAME_LEN != sizeof(cfg->name)); in efx_mcdi_get_phy_cfg()
30 rc = -EIO; in efx_mcdi_get_phy_cfg()
34 cfg->flags = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_FLAGS); in efx_mcdi_get_phy_cfg()
35 cfg->type = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_TYPE); in efx_mcdi_get_phy_cfg()
36 cfg->supported_cap = in efx_mcdi_get_phy_cfg()
38 cfg->channel = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_CHANNEL); in efx_mcdi_get_phy_cfg()
39 cfg->port = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_PRT); in efx_mcdi_get_phy_cfg()
40 cfg->stats_mask = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_STATS_MASK); in efx_mcdi_get_phy_cfg()
41 memcpy(cfg->name, MCDI_PTR(outbuf, GET_PHY_CFG_OUT_NAME), in efx_mcdi_get_phy_cfg()
[all …]

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