1*8da35245SBin Meng /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
291975b0fSHaavard Skinnemoen /*
391975b0fSHaavard Skinnemoen * linux/mii.h: definitions for MII-compatible transceivers
491975b0fSHaavard Skinnemoen * Originally drivers/net/sunhme.h.
591975b0fSHaavard Skinnemoen *
691975b0fSHaavard Skinnemoen * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com)
791975b0fSHaavard Skinnemoen */
891975b0fSHaavard Skinnemoen
991975b0fSHaavard Skinnemoen #ifndef __LINUX_MII_H__
1091975b0fSHaavard Skinnemoen #define __LINUX_MII_H__
1191975b0fSHaavard Skinnemoen
1291975b0fSHaavard Skinnemoen /* Generic MII registers. */
1391975b0fSHaavard Skinnemoen #define MII_BMCR 0x00 /* Basic mode control register */
1491975b0fSHaavard Skinnemoen #define MII_BMSR 0x01 /* Basic mode status register */
1591975b0fSHaavard Skinnemoen #define MII_PHYSID1 0x02 /* PHYS ID 1 */
1691975b0fSHaavard Skinnemoen #define MII_PHYSID2 0x03 /* PHYS ID 2 */
1791975b0fSHaavard Skinnemoen #define MII_ADVERTISE 0x04 /* Advertisement control reg */
1891975b0fSHaavard Skinnemoen #define MII_LPA 0x05 /* Link partner ability reg */
1991975b0fSHaavard Skinnemoen #define MII_EXPANSION 0x06 /* Expansion register */
207ea23555SMacpaul Lin #define MII_CTRL1000 0x09 /* 1000BASE-T control */
217ea23555SMacpaul Lin #define MII_STAT1000 0x0a /* 1000BASE-T status */
22*8da35245SBin Meng #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
23*8da35245SBin Meng #define MII_MMD_DATA 0x0e /* MMD Access Data Register */
247ea23555SMacpaul Lin #define MII_ESTATUS 0x0f /* Extended Status */
2591975b0fSHaavard Skinnemoen #define MII_DCOUNTER 0x12 /* Disconnect counter */
2691975b0fSHaavard Skinnemoen #define MII_FCSCOUNTER 0x13 /* False carrier counter */
2791975b0fSHaavard Skinnemoen #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
2891975b0fSHaavard Skinnemoen #define MII_RERRCOUNTER 0x15 /* Receive error counter */
2991975b0fSHaavard Skinnemoen #define MII_SREVISION 0x16 /* Silicon revision */
3091975b0fSHaavard Skinnemoen #define MII_RESV1 0x17 /* Reserved... */
3191975b0fSHaavard Skinnemoen #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
3291975b0fSHaavard Skinnemoen #define MII_PHYADDR 0x19 /* PHY address */
3391975b0fSHaavard Skinnemoen #define MII_RESV2 0x1a /* Reserved... */
3491975b0fSHaavard Skinnemoen #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
3591975b0fSHaavard Skinnemoen #define MII_NCONFIG 0x1c /* Network interface config */
3691975b0fSHaavard Skinnemoen
3791975b0fSHaavard Skinnemoen /* Basic mode control register. */
3891975b0fSHaavard Skinnemoen #define BMCR_RESV 0x003f /* Unused... */
3991975b0fSHaavard Skinnemoen #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
4091975b0fSHaavard Skinnemoen #define BMCR_CTST 0x0080 /* Collision test */
4191975b0fSHaavard Skinnemoen #define BMCR_FULLDPLX 0x0100 /* Full duplex */
4291975b0fSHaavard Skinnemoen #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
43*8da35245SBin Meng #define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */
44*8da35245SBin Meng #define BMCR_PDOWN 0x0800 /* Enable low power state */
4591975b0fSHaavard Skinnemoen #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
4691975b0fSHaavard Skinnemoen #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
4791975b0fSHaavard Skinnemoen #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
48*8da35245SBin Meng #define BMCR_RESET 0x8000 /* Reset to default state */
49*8da35245SBin Meng #define BMCR_SPEED10 0x0000 /* Select 10Mbps */
5091975b0fSHaavard Skinnemoen
5191975b0fSHaavard Skinnemoen /* Basic mode status register. */
5291975b0fSHaavard Skinnemoen #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
5391975b0fSHaavard Skinnemoen #define BMSR_JCD 0x0002 /* Jabber detected */
5491975b0fSHaavard Skinnemoen #define BMSR_LSTATUS 0x0004 /* Link status */
5591975b0fSHaavard Skinnemoen #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
5691975b0fSHaavard Skinnemoen #define BMSR_RFAULT 0x0010 /* Remote fault detected */
5791975b0fSHaavard Skinnemoen #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
587ea23555SMacpaul Lin #define BMSR_RESV 0x00c0 /* Unused... */
597ea23555SMacpaul Lin #define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
607ea23555SMacpaul Lin #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
617ea23555SMacpaul Lin #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
6291975b0fSHaavard Skinnemoen #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
6391975b0fSHaavard Skinnemoen #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
6491975b0fSHaavard Skinnemoen #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
6591975b0fSHaavard Skinnemoen #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
6691975b0fSHaavard Skinnemoen #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
6791975b0fSHaavard Skinnemoen
6891975b0fSHaavard Skinnemoen /* Advertisement control register. */
6991975b0fSHaavard Skinnemoen #define ADVERTISE_SLCT 0x001f /* Selector bits */
7091975b0fSHaavard Skinnemoen #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
7191975b0fSHaavard Skinnemoen #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
727ea23555SMacpaul Lin #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
7391975b0fSHaavard Skinnemoen #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
747ea23555SMacpaul Lin #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
7591975b0fSHaavard Skinnemoen #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
767ea23555SMacpaul Lin #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
7791975b0fSHaavard Skinnemoen #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
787ea23555SMacpaul Lin #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
7991975b0fSHaavard Skinnemoen #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
807ea23555SMacpaul Lin #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
817ea23555SMacpaul Lin #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
827ea23555SMacpaul Lin #define ADVERTISE_RESV 0x1000 /* Unused... */
8391975b0fSHaavard Skinnemoen #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
8491975b0fSHaavard Skinnemoen #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
8591975b0fSHaavard Skinnemoen #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
8691975b0fSHaavard Skinnemoen
8791975b0fSHaavard Skinnemoen #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
8891975b0fSHaavard Skinnemoen ADVERTISE_CSMA)
8991975b0fSHaavard Skinnemoen #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
9091975b0fSHaavard Skinnemoen ADVERTISE_100HALF | ADVERTISE_100FULL)
9191975b0fSHaavard Skinnemoen
9291975b0fSHaavard Skinnemoen /* Link partner ability register. */
9391975b0fSHaavard Skinnemoen #define LPA_SLCT 0x001f /* Same as advertise selector */
9491975b0fSHaavard Skinnemoen #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
957ea23555SMacpaul Lin #define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
9691975b0fSHaavard Skinnemoen #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
977ea23555SMacpaul Lin #define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
9891975b0fSHaavard Skinnemoen #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
997ea23555SMacpaul Lin #define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
10091975b0fSHaavard Skinnemoen #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
1017ea23555SMacpaul Lin #define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
10291975b0fSHaavard Skinnemoen #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
1037ea23555SMacpaul Lin #define LPA_PAUSE_CAP 0x0400 /* Can pause */
1047ea23555SMacpaul Lin #define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
1057ea23555SMacpaul Lin #define LPA_RESV 0x1000 /* Unused... */
10691975b0fSHaavard Skinnemoen #define LPA_RFAULT 0x2000 /* Link partner faulted */
10791975b0fSHaavard Skinnemoen #define LPA_LPACK 0x4000 /* Link partner acked us */
10891975b0fSHaavard Skinnemoen #define LPA_NPAGE 0x8000 /* Next page bit */
10991975b0fSHaavard Skinnemoen
11091975b0fSHaavard Skinnemoen #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
11191975b0fSHaavard Skinnemoen #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
11291975b0fSHaavard Skinnemoen
11391975b0fSHaavard Skinnemoen /* Expansion register for auto-negotiation. */
11491975b0fSHaavard Skinnemoen #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
11591975b0fSHaavard Skinnemoen #define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
11691975b0fSHaavard Skinnemoen #define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
11791975b0fSHaavard Skinnemoen #define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
11891975b0fSHaavard Skinnemoen #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
11991975b0fSHaavard Skinnemoen #define EXPANSION_RESV 0xffe0 /* Unused... */
12091975b0fSHaavard Skinnemoen
121de1d786eSCharles Coldwell #define ESTATUS_1000_XFULL 0x8000 /* Can do 1000BX Full */
122de1d786eSCharles Coldwell #define ESTATUS_1000_XHALF 0x4000 /* Can do 1000BX Half */
1237ea23555SMacpaul Lin #define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
1247ea23555SMacpaul Lin #define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
1257ea23555SMacpaul Lin
12691975b0fSHaavard Skinnemoen /* N-way test register. */
12791975b0fSHaavard Skinnemoen #define NWAYTEST_RESV1 0x00ff /* Unused... */
12891975b0fSHaavard Skinnemoen #define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
12991975b0fSHaavard Skinnemoen #define NWAYTEST_RESV2 0xfe00 /* Unused... */
13091975b0fSHaavard Skinnemoen
1317ea23555SMacpaul Lin /* 1000BASE-T Control register */
1327ea23555SMacpaul Lin #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
1337ea23555SMacpaul Lin #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
134*8da35245SBin Meng #define CTL1000_AS_MASTER 0x0800
135*8da35245SBin Meng #define CTL1000_ENABLE_MASTER 0x1000
1367ea23555SMacpaul Lin
1377ea23555SMacpaul Lin /* 1000BASE-T Status register */
1387ea23555SMacpaul Lin #define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
1397ea23555SMacpaul Lin #define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
1407ea23555SMacpaul Lin #define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
1417ea23555SMacpaul Lin #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
1427ea23555SMacpaul Lin
1437ea23555SMacpaul Lin /* Flow control flags */
1447ea23555SMacpaul Lin #define FLOW_CTRL_TX 0x01
1457ea23555SMacpaul Lin #define FLOW_CTRL_RX 0x02
14691975b0fSHaavard Skinnemoen
147*8da35245SBin Meng /* MMD Access Control register fields */
148*8da35245SBin Meng #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/
149*8da35245SBin Meng #define MII_MMD_CTRL_ADDR 0x0000 /* Address */
150*8da35245SBin Meng #define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */
151*8da35245SBin Meng #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
152*8da35245SBin Meng #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
153*8da35245SBin Meng
15491975b0fSHaavard Skinnemoen /**
15591975b0fSHaavard Skinnemoen * mii_nway_result
15691975b0fSHaavard Skinnemoen * @negotiated: value of MII ANAR and'd with ANLPAR
15791975b0fSHaavard Skinnemoen *
15891975b0fSHaavard Skinnemoen * Given a set of MII abilities, check each bit and returns the
15991975b0fSHaavard Skinnemoen * currently supported media, in the priority order defined by
16091975b0fSHaavard Skinnemoen * IEEE 802.3u. We use LPA_xxx constants but note this is not the
16191975b0fSHaavard Skinnemoen * value of LPA solely, as described above.
16291975b0fSHaavard Skinnemoen *
16391975b0fSHaavard Skinnemoen * The one exception to IEEE 802.3u is that 100baseT4 is placed
16491975b0fSHaavard Skinnemoen * between 100T-full and 100T-half. If your phy does not support
16591975b0fSHaavard Skinnemoen * 100T4 this is fine. If your phy places 100T4 elsewhere in the
16691975b0fSHaavard Skinnemoen * priority order, you will need to roll your own function.
16791975b0fSHaavard Skinnemoen */
mii_nway_result(unsigned int negotiated)16891975b0fSHaavard Skinnemoen static inline unsigned int mii_nway_result (unsigned int negotiated)
16991975b0fSHaavard Skinnemoen {
17091975b0fSHaavard Skinnemoen unsigned int ret;
17191975b0fSHaavard Skinnemoen
17291975b0fSHaavard Skinnemoen if (negotiated & LPA_100FULL)
17391975b0fSHaavard Skinnemoen ret = LPA_100FULL;
17491975b0fSHaavard Skinnemoen else if (negotiated & LPA_100BASE4)
17591975b0fSHaavard Skinnemoen ret = LPA_100BASE4;
17691975b0fSHaavard Skinnemoen else if (negotiated & LPA_100HALF)
17791975b0fSHaavard Skinnemoen ret = LPA_100HALF;
17891975b0fSHaavard Skinnemoen else if (negotiated & LPA_10FULL)
17991975b0fSHaavard Skinnemoen ret = LPA_10FULL;
18091975b0fSHaavard Skinnemoen else
18191975b0fSHaavard Skinnemoen ret = LPA_10HALF;
18291975b0fSHaavard Skinnemoen
18391975b0fSHaavard Skinnemoen return ret;
18491975b0fSHaavard Skinnemoen }
18591975b0fSHaavard Skinnemoen
18691975b0fSHaavard Skinnemoen /**
18791975b0fSHaavard Skinnemoen * mii_duplex
18891975b0fSHaavard Skinnemoen * @duplex_lock: Non-zero if duplex is locked at full
18991975b0fSHaavard Skinnemoen * @negotiated: value of MII ANAR and'd with ANLPAR
19091975b0fSHaavard Skinnemoen *
19191975b0fSHaavard Skinnemoen * A small helper function for a common case. Returns one
19291975b0fSHaavard Skinnemoen * if the media is operating or locked at full duplex, and
19391975b0fSHaavard Skinnemoen * returns zero otherwise.
19491975b0fSHaavard Skinnemoen */
mii_duplex(unsigned int duplex_lock,unsigned int negotiated)19591975b0fSHaavard Skinnemoen static inline unsigned int mii_duplex (unsigned int duplex_lock,
19691975b0fSHaavard Skinnemoen unsigned int negotiated)
19791975b0fSHaavard Skinnemoen {
19891975b0fSHaavard Skinnemoen if (duplex_lock)
19991975b0fSHaavard Skinnemoen return 1;
20091975b0fSHaavard Skinnemoen if (mii_nway_result(negotiated) & LPA_DUPLEX)
20191975b0fSHaavard Skinnemoen return 1;
20291975b0fSHaavard Skinnemoen return 0;
20391975b0fSHaavard Skinnemoen }
20491975b0fSHaavard Skinnemoen
2051c1e3700SYuiko Oshino /**
2061c1e3700SYuiko Oshino * mii_resolve_flowctrl_fdx
2071c1e3700SYuiko Oshino * @lcladv: value of MII ADVERTISE register
2081c1e3700SYuiko Oshino * @rmtadv: value of MII LPA register
2091c1e3700SYuiko Oshino *
2101c1e3700SYuiko Oshino * Resolve full duplex flow control as per IEEE 802.3-2005 table 28B-3
2111c1e3700SYuiko Oshino */
mii_resolve_flowctrl_fdx(u16 lcladv,u16 rmtadv)2121c1e3700SYuiko Oshino static inline u8 mii_resolve_flowctrl_fdx(u16 lcladv, u16 rmtadv)
2131c1e3700SYuiko Oshino {
2141c1e3700SYuiko Oshino u8 cap = 0;
2151c1e3700SYuiko Oshino
2161c1e3700SYuiko Oshino if (lcladv & rmtadv & ADVERTISE_PAUSE_CAP) {
2171c1e3700SYuiko Oshino cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
2181c1e3700SYuiko Oshino } else if (lcladv & rmtadv & ADVERTISE_PAUSE_ASYM) {
2191c1e3700SYuiko Oshino if (lcladv & ADVERTISE_PAUSE_CAP)
2201c1e3700SYuiko Oshino cap = FLOW_CTRL_RX;
2211c1e3700SYuiko Oshino else if (rmtadv & ADVERTISE_PAUSE_CAP)
2221c1e3700SYuiko Oshino cap = FLOW_CTRL_TX;
2231c1e3700SYuiko Oshino }
2241c1e3700SYuiko Oshino
2251c1e3700SYuiko Oshino return cap;
2261c1e3700SYuiko Oshino }
2271c1e3700SYuiko Oshino
22891975b0fSHaavard Skinnemoen #endif /* __LINUX_MII_H__ */
229