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/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Davia-hx711.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/avia-hx711.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andreas Klinger <ak@it-klinger.de>
13 Bit-banging driver using two GPIOs:
14 - sck-gpio gives a clock to the sensor with 24 cycles for data retrieval
17 - dout-gpio is the sensor data the sensor responds to the clock
25 - avia,hx711
27 sck-gpios:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/siox/
H A Deckelmann,siox-gpio.txt4 - compatible : "eckelmann,siox-gpio"
5 - din-gpios, dout-gpios, dclk-gpios, dld-gpios: references gpios for the
11 compatible = "eckelmann,siox-gpio";
12 pinctrl-names = "default";
13 pinctrl-0 = <&pinctrl_siox>;
15 din-gpios = <&gpio6 11 0>;
16 dout-gpios = <&gpio6 8 0>;
17 dclk-gpios = <&gpio6 9 0>;
18 dld-gpios = <&gpio6 10 0>;
/openbmc/linux/drivers/pinctrl/starfive/
H A Dpinctrl-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0
26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
29 #include "../pinctrl-utils.h"
33 #define DRIVER_NAME "pinctrl-starfive"
37 * https://github.com/starfive-tech/JH7100_Docs
48 * The following 32-bit registers come in pairs, but only the offset of the
49 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
50 * the second GPIO 32-63.
54 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
55 * interrupt is level-triggered.
[all …]
H A Dpinctrl-starfive-jh7110.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/pinctrl/pinconf-generic.h>
17 struct pinctrl_gpio_range gpios; member
43 /* gpio dout/doen/din/gpioinput register */
59 unsigned int din, u32 dout,
69 unsigned int din, u32 dout, u32 doen);
H A Dpinctrl-starfive-jh7110.c1 // SPDX-License-Identifier: GPL-2.0
27 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
30 #include "../pinctrl-utils.h"
33 #include "pinctrl-starfive-jh7110.h"
52 * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
53 * | din | dout | doen | function | pin |
100 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_pin_dbg_show()
102 seq_printf(s, "%s", dev_name(pctldev->dev)); in jh7110_pin_dbg_show()
104 if (pin < sfp->gc.ngpio) { in jh7110_pin_dbg_show()
107 u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset); in jh7110_pin_dbg_show() local
[all …]
/openbmc/u-boot/drivers/spi/
H A Dmxc_spi.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
15 #include <asm/mach-imx/spi.h>
29 return -1; in board_spi_cs_gpio()
63 dm_gpio_set_value(&mxcs->ss, 1); in mxc_spi_cs_activate()
65 if (mxcs->gpio > 0) in mxc_spi_cs_activate()
66 gpio_set_value(mxcs->gpio, mxcs->ss_pol); in mxc_spi_cs_activate()
73 dm_gpio_set_value(&mxcs->ss, 0); in mxc_spi_cs_deactivate()
75 if (mxcs->gpio > 0) in mxc_spi_cs_deactivate()
76 gpio_set_value(mxcs->gpio, !(mxcs->ss_pol)); in mxc_spi_cs_deactivate()
[all …]
H A Dsoft_spi.c1 // SPDX-License-Identifier: GPL-2.0+
43 dm_gpio_set_value(&plat->sclk, bit); in soft_spi_scl()
53 dm_gpio_set_value(&plat->mosi, bit); in soft_spi_sda()
63 dm_gpio_set_value(&plat->cs, 0); in soft_spi_cs_activate()
64 dm_gpio_set_value(&plat->sclk, 0); in soft_spi_cs_activate()
65 dm_gpio_set_value(&plat->cs, 1); in soft_spi_cs_activate()
75 dm_gpio_set_value(&plat->cs, 0); in soft_spi_cs_deactivate()
95 /*-----------------------------------------------------------------------
101 * The source of the outgoing bits is the "dout" parameter and the
102 * destination of the input bits is the "din" parameter. Note that "dout"
[all …]
H A Datmel_spi.c1 // SPDX-License-Identifier: GPL-2.0+
72 scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz; in spi_setup_slave()
90 as->regs = regs; in spi_setup_slave()
91 as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS in spi_setup_slave()
94 as->mr |= ATMEL_SPI_MR_WDRBT; in spi_setup_slave()
98 return &as->slave; in spi_setup_slave()
119 spi_writel(as, MR, as->mr); in spi_claim_bus()
133 const void *dout, void *din, unsigned long flags) in spi_xfer() argument
140 const u8 *txp = dout; in spi_xfer()
149 * TODO: The controller can do non-multiple-of-8 bit in spi_xfer()
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/
H A Dgpio.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
14 * mvebu_config_gpio - GPIO configuration
24 /* Init GPIOS to default values as per board requirement */ in mvebu_config_gpio()
25 writel(gpp0_oe_val, &gpio0reg->dout); in mvebu_config_gpio()
26 writel(gpp1_oe_val, &gpio1reg->dout); in mvebu_config_gpio()
27 writel(gpp0_oe, &gpio0reg->oe); in mvebu_config_gpio()
28 writel(gpp1_oe, &gpio1reg->oe); in mvebu_config_gpio()
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6dl-eckelmann-ci4x10.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
15 compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl";
18 stdout-path = &uart3;
26 rmii_clk: clock-rmii {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <50000000>;
31 clock-output-names = "enet_ref_pad";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dmaxim,max98925.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ryan Lee <ryans.lee@maximintegrated.com>
15 - maxim,max98925
16 - maxim,max98926
17 - maxim,max98927
22 reset-gpios:
25 '#sound-dai-cells':
28 vmon-slot-no:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/panel/
H A Dpanel-mipi-dbi-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Noralf Trønnes <noralf@tronnes.org>
23 - Power:
24 - Vdd: Power supply for display module
25 Called power-supply in this binding.
26 - Vddi: Logic level supply for interface signals
27 Called io-supply in this binding.
[all …]
/openbmc/u-boot/board/CZ.NIC/turris_mox/
H A Dturris_mox.c1 // SPDX-License-Identifier: GPL-2.0+
46 gd->ram_base = 0; in dram_init()
47 gd->ram_size = (phys_size_t)get_ram_size(0, 0x40000000); in dram_init()
54 gd->bd->bi_dram[0].start = (phys_addr_t)0; in dram_init_banksize()
55 gd->bd->bi_dram[0].size = gd->ram_size; in dram_init_banksize()
69 * if pcie should be enabled in U-Boot's device tree. Therefore we have in board_fix_fdt()
107 printf("Cannot find PCIe node in U-Boot's device tree!\n"); in board_fix_fdt()
113 printf("Cannot %s PCIe in U-Boot's device tree!\n", in board_fix_fdt()
146 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
188 static u8 topology[MAX_MOX_MODULES - 1]; in mox_get_topology()
[all …]
/openbmc/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1-nezha.dts1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
7 * The Nezha-D1 has a 40-pin IO header. Some of these pins are routed
8 * directly to pads on the SoC, others come from an 8-bit pcf857x IO
12 * Lines which are routed to the 40-pin header are named as follows:
15 * <pin#> is the actual pin number of the 40-pin header
20 * http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf
23 #include <dt-bindings/gpio/gpio.h>
24 #include <dt-bindings/input/input.h>
26 /dts-v1/;
[all …]
/openbmc/linux/arch/microblaze/boot/dts/
H A Dsystem.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2007-2008 Xilinx, Inc.
6 * (C) Copyright 2007-2009 Michal Simek
13 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
16 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 stdout-path = "/plb@0/serial@84000000";
35 #address-cells = <1>;
37 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
22 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
33 led-stat {
34 label = "nanopi-k2:blue:stat";
[all …]
H A Dmeson-gxl-s905x-khadas-vim.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxl-s905x-p212.dtsi"
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl";
16 adc-keys {
17 compatible = "adc-keys";
18 io-channels = <&saradc 0>;
19 io-channel-names = "buttons";
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
12 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
20 stdout-path = "serial0:115200n8";
29 compatible = "gpio-leds";
32 label = "nanopi-k2:blue:stat";
33 gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
34 default-state = "on";
[all …]
H A Dmeson-gxl-s905x-khadas-vim.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
10 #include "meson-gxl-s905x-p212.dtsi"
13 compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl";
16 adc-keys {
17 compatible = "adc-keys";
18 io-channels = <&saradc 0>;
19 io-channel-names = "buttons";
20 keyup-threshold-microvolt = <1710000>;
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-max730x.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * 28 GPIOs. 8 of them can trigger an interrupt. See datasheet for more
11 * - DIN must be stable at the rising edge of clock.
12 * - when writing:
13 * - always clock in 16 clocks at once
14 * - at DIN: D15 first, D0 last
15 * - D0..D7 = databyte, D8..D14 = commandbyte
16 * - D15 = low -> write command
17 * - when reading
18 * - always clock in 16 clocks at once
[all …]
H A Dgpio-xilinx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2008 - 2013 Xilinx, Inc.
45 * struct xgpio_instance - Stores information about GPIO device
79 return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64); in xgpio_from_bit()
84 return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64); in xgpio_to_bit()
112 return -EINVAL; in xgpio_regoffset()
118 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); in xgpio_read_ch()
125 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); in xgpio_write_ch()
132 int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1); in xgpio_read_ch_all()
140 int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1); in xgpio_write_ch_all()
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-apalis-v1.2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2016-2018 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
21 avddio-pex-supply = <&reg_1v05_vdd>;
22 avdd-pex-pll-supply = <&reg_1v05_vdd>;
23 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
24 dvddio-pex-supply = <&reg_1v05_vdd>;
25 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
26 hvdd-pex-supply = <&reg_module_3v3>;
27 vddio-pex-ctl-supply = <&reg_module_3v3>;
[all …]
H A Dtegra124-apalis.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
20 avddio-pex-supply = <&reg_1v05_vdd>;
21 avdd-pex-pll-supply = <&reg_1v05_vdd>;
22 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
23 dvddio-pex-supply = <&reg_1v05_vdd>;
24 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
25 hvdd-pex-supply = <&reg_module_3v3>;
26 vddio-pex-ctl-supply = <&reg_module_3v3>;
[all …]
/openbmc/linux/drivers/mfd/
H A Dtps65010.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * tps65010 - driver for tps6501x power management chips
6 * Copyright (C) 2004-2005 David Brownell
27 /*-------------------------------------------------------------------------*/
37 /*-------------------------------------------------------------------------*/
40 * voltage regulators, lithium ion/polymer battery charging, GPIOs, LEDs,
47 * battery-insert != device-on.
84 /*-------------------------------------------------------------------------*/
184 struct tps65010 *tps = s->private; in dbg_show()
190 switch (tps->model) { in dbg_show()
[all …]
/openbmc/linux/drivers/iio/adc/
H A Dad4130.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
125 #define AD4130_INVALID_SLOT -1
137 [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3,
138 [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2,
139 [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
140 [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
141 [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
319 [AD4130_INT_PIN_DOUT] = "dout",
393 return -EINVAL; in ad4130_get_reg_size()
[all …]

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