1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2d0787656SStefan Roese /*
3d0787656SStefan Roese * (C) Copyright 2009
4d0787656SStefan Roese * Marvell Semiconductor <www.marvell.com>
5d0787656SStefan Roese * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6d0787656SStefan Roese */
7d0787656SStefan Roese
8d0787656SStefan Roese #include <common.h>
9d0787656SStefan Roese #include <asm/io.h>
10d0787656SStefan Roese #include <asm/arch/cpu.h>
11d0787656SStefan Roese #include <asm/arch/soc.h>
12d0787656SStefan Roese
13d0787656SStefan Roese /*
14d0787656SStefan Roese * mvebu_config_gpio - GPIO configuration
15d0787656SStefan Roese */
mvebu_config_gpio(u32 gpp0_oe_val,u32 gpp1_oe_val,u32 gpp0_oe,u32 gpp1_oe)16d0787656SStefan Roese void mvebu_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val,
17d0787656SStefan Roese u32 gpp0_oe, u32 gpp1_oe)
18d0787656SStefan Roese {
19d0787656SStefan Roese struct kwgpio_registers *gpio0reg =
20d0787656SStefan Roese (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
21d0787656SStefan Roese struct kwgpio_registers *gpio1reg =
22d0787656SStefan Roese (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
23d0787656SStefan Roese
24d0787656SStefan Roese /* Init GPIOS to default values as per board requirement */
25d0787656SStefan Roese writel(gpp0_oe_val, &gpio0reg->dout);
26d0787656SStefan Roese writel(gpp1_oe_val, &gpio1reg->dout);
27d0787656SStefan Roese writel(gpp0_oe, &gpio0reg->oe);
28d0787656SStefan Roese writel(gpp1_oe, &gpio1reg->oe);
29d0787656SStefan Roese }
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