| /openbmc/linux/Documentation/devicetree/bindings/display/imx/ |
| H A D | nxp,imx8mq-dcss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
23 const: nxp,imx8mq-dcss
27 - description: DCSS base address and size, up to IRQ steer start
28 - description: DCSS BLKCTL base address and size
32 - description: Context loader completion and error interrupt
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | brcm,kona-ccu.txt | 4 clock control units (CCUs). A CCU is a clock provider that manages
5 a set of clock signals. Each CCU is represented by a node in the
8 This binding uses the common clock binding:
9 Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible
13 Shall have a value of the form "brcm,<model>-<which>-ccu",
16 "brcm,bcm11351-root-ccu"
19 - reg
21 containing clock control registers
22 - #clock-cells
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| H A D | renesas,rzg2l-cpg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
15 similar, but does not have Clock Monitor Registers.
18 - The CPG block generates various core clocks,
19 - The Module Standby Mode block provides two functions:
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| H A D | moxa,moxart-clock.txt | 1 Device Tree Clock bindings for arch-moxart
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - compatible : Must be "moxa,moxart-pll-clock"
15 - #clock-cells : Should be 0
16 - reg : Should contain registers location and length
17 - clocks : Should contain phandle + clock-specifier for the parent clock
20 - clock-output-names : Should contain clock name
26 - compatible : Must be "moxa,moxart-apb-clock"
27 - #clock-cells : Should be 0
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| H A D | renesas,cpg-mssr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator / Module Standby and Software Reset
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
18 - The CPG block generates various core clocks,
19 - The MSSR block provides two functions:
20 1. Module Standby, providing a Clock Domain to control the clock supply
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | nokia-bluetooth.txt | 2 ---------------------
13 - compatible: should contain "nokia,h4p-bluetooth" as well as one of the following:
14 * "brcm,bcm2048-nokia"
15 * "ti,wl1271-bluetooth-nokia"
16 - reset-gpios: GPIO specifier, used to reset the BT module (active low)
17 - bluetooth-wakeup-gpios: GPIO specifier, used to wakeup the BT module (active high)
18 - host-wakeup-gpios: GPIO specifier, used to wakeup the host processor (active high)
19 - clock-names: should be "sysclk"
20 - clocks: should contain a clock specifier for every name in clock-names
24 - None
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| H A D | broadcom-bluetooth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/broadcom-bluetooth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 This binding describes Broadcom UART-attached bluetooth chips.
18 - brcm,bcm20702a1
19 - brcm,bcm4329-bt
20 - brcm,bcm4330-bt
21 - brcm,bcm4334-bt
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| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | hisilicon,histb-xhci.txt | 6 - compatible: should be "hisilicon,hi3798cv200-xhci"
7 - reg: specifies physical base address and size of the registers
8 - interrupts : interrupt used by the controller
9 - clocks: a list of phandle + clock-specifier pairs, one for each
10 entry in clock-names
11 - clock-names: must contain
12 "bus": for bus clock
13 "utmi": for utmi clock
14 "pipe": for pipe clock
15 "suspend": for suspend clock
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| H A D | msm-hsusb.txt | 6 - compatible: Should contain "qcom,ehci-host"
7 - regs: offset and length of the register set in the memory map
8 - usb-phy: phandle for the PHY device
13 compatible = "qcom,ehci-host";
15 usb-phy = <&usb_otg>;
21 - compatible: Should contain:
22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
25 - regs: Offset and length of the register set in the memory map
26 - interrupts: interrupt-specifier for the OTG interrupt.
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| /openbmc/u-boot/doc/device-tree-bindings/serial/ |
| H A D | omap_serial.txt | 4 - compatible : should be "ti,omap2-uart" for OMAP2 controllers
5 - compatible : should be "ti,omap3-uart" for OMAP3 controllers
6 - compatible : should be "ti,omap4-uart" for OMAP4 controllers
7 - compatible : should be "ti,am4372-uart" for AM437x controllers
8 - compatible : should be "ti,am3352-uart" for AM335x controllers
9 - compatible : should be "ti,dra742-uart" for DRA7x controllers
10 - reg : address and length of the register space
11 - interrupts or interrupts-extended : Should contain the uart interrupt
12 specifier or both the interrupt
14 specifier.
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | hisilicon-histb-pcie.txt | 6 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
11 - compatible: Should be one of the following strings:
12 "hisilicon,hi3798cv200-pcie"
13 - reg: Should contain sysctl, rc_dbi, config registers location and length.
14 - reg-names: Must include the following entries:
16 "rc-dbi": configuration space of PCIe controller;
18 - bus-range: PCI bus numbers covered.
19 - interrupts: MSI interrupt.
20 - interrupt-names: Must include "msi" entries.
21 - clocks: List of phandle and clock specifier pairs as listed in clock-names
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | phy-rockchip-typec.txt | 1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
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| H A D | phy-rockchip-inno-hdmi.txt | 4 - compatible : should be one of the listed compatibles:
5 * "rockchip,rk3228-hdmi-phy",
6 * "rockchip,rk3328-hdmi-phy";
7 - reg : Address and length of the hdmi phy control register set
8 - clocks : phandle + clock specifier for the phy clocks
9 - clock-names : string, clock name, must contain "sysclk" for system
10 control and register configuration, "refoclk" for crystal-
11 oscillator reference PLL clock input and "refpclk" for pclk-
12 based refeference PLL clock input.
13 - #clock-cells: should be 0.
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| /openbmc/linux/Documentation/devicetree/bindings/ata/ |
| H A D | ahci-mtk.txt | 4 - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
5 When using "mediatek,mtk-ahci" compatible strings, you
7 - "mediatek,mt7622-ahci"
8 - reg : Physical base addresses and length of register sets.
9 - interrupts : Interrupt associated with the SATA device.
10 - interrupt-names : Associated name must be: "hostc".
11 - clocks : A list of phandle and clock specifier pairs, one for each
12 entry in clock-names.
13 - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
14 - phys : A phandle and PHY specifier pair for the PHY port.
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| H A D | ahci-dm816.txt | 2 ---------------------------------------------------------
5 - compatible: must be "ti,dm816-ahci"
6 - reg: physical base address and size of the register region used by
8 - interrupts: interrupt specifier (refer to the interrupt binding)
9 - clocks: list of phandle and clock specifier pairs (or only
10 phandles for clock providers with '0' defined for
11 #clock-cells); two clocks must be specified: the functional
12 clock and an external reference clock
17 compatible = "ti,dm816-ahci";
|
| H A D | ahci-fsl-qoriq.txt | 4 - reg: Physical base address and size of the controller's register area.
5 - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
7 - clocks: Input clock specifier. Refer to common clock bindings.
8 - interrupts: Interrupt specifier. Refer to interrupt binding.
11 - dma-coherent: Enable AHCI coherent DMA operation.
12 - reg-names: register area names when there are more than 1 register area.
16 compatible = "fsl,ls1021a-ahci";
20 dma-coherent;
|
| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | hix5hd2-ir.txt | 1 Device-Tree bindings for hix5hd2 ir IP
4 - compatible: Should contain "hisilicon,hix5hd2-ir", or:
5 - "hisilicon,hi3796cv300-ir" for Hi3796CV300 IR device.
6 - reg: Base physical address of the controller and length of memory
8 - interrupts: interrupt-specifier for the sole interrupt generated by
9 the device. The interrupt specifier format depends on the interrupt
11 - clocks: clock phandle and specifier pair.
14 - linux,rc-map-name: see rc.txt file in the same directory.
15 - hisilicon,power-syscon: DEPRECATED. Don't use this in new dts files.
21 compatible = "hisilicon,hix5hd2-ir";
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| /openbmc/u-boot/doc/device-tree-bindings/phy/ |
| H A D | phy-stm32-usbphyc.txt | 14 |_ PHY port#2 ----| |________________
23 - compatible: must be "st,stm32mp1-usbphyc"
24 - reg: address and length of the usb phy control register set
25 - clocks: phandle + clock specifier for the PLL phy clock
26 - #address-cells: number of address cells for phys sub-nodes, must be <1>
27 - #size-cells: number of size cells for phys sub-nodes, must be <0>
30 - assigned-clocks: phandle + clock specifier for the PLL phy clock
31 - assigned-clock-parents: the PLL phy clock parent
32 - resets: phandle + reset specifier
34 Required nodes: one sub-node per port the controller provides.
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| /openbmc/linux/Documentation/devicetree/bindings/hsi/ |
| H A D | omap-ssi.txt | 9 - compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi"
10 - reg-names: Contains the values "sys" and "gdd" (in this order).
11 - reg: Contains a matching register specifier for each entry
12 in reg-names.
13 - interrupt-names: Contains the value "gdd_mpu".
14 - interrupts: Contains matching interrupt information for each entry
15 in interrupt-names.
16 - ranges: Represents the bus address mapping between the main
18 - clock-names: Must include the following entries:
19 "ssi_ssr_fck": The OMAP clock of that name
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| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | adi,axi-spdif-tx.txt | 1 ADI AXI-SPDIF controller
4 - compatible : Must be "adi,axi-spdif-tx-1.00.a"
5 - reg : Must contain SPDIF core's registers location and length
6 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
7 The controller expects two clocks, the clock used for the AXI interface and
8 the clock used as the sampling rate reference clock sample.
9 - clock-names: "axi" for the clock to the AXI interface, "ref" for the sample
10 rate reference clock.
11 - dmas: Pairs of phandle and specifier for the DMA channel that is used by
13 - dma-names : Must be "tx"
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| H A D | adi,axi-i2s.txt | 1 ADI AXI-I2S controller
7 - compatible : Must be "adi,axi-i2s-1.00.a"
8 - reg : Must contain I2S core's registers location and length
9 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
10 The controller expects two clocks, the clock used for the AXI interface and
11 the clock used as the sampling rate reference clock sample.
12 - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
13 rate reference clock.
14 - dmas: Pairs of phandle and specifier for the DMA channels that are used by
17 - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
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| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | vexpress-config.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/vexpress-config.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andre Przywara <andre.przywara@arm.com>
16 function and device numbers - see motherboard's TRM for more details.
20 const: arm,vexpress,config-bus
22 arm,vexpress,config-bridge:
31 const: arm,vexpress-muxfpga
33 arm,vexpress-sysreg,func:
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| /openbmc/linux/Documentation/devicetree/bindings/dma/ |
| H A D | sprd-dma.txt | 6 - compatible: Should be "sprd,sc9860-dma".
7 - reg: Should contain DMA registers location and length.
8 - interrupts: Should contain one interrupt shared by all channel.
9 - #dma-cells: must be <1>. Used to represent the number of integer
11 - dma-channels : Number of DMA channels supported. Should be 32.
12 - clock-names: Should contain the clock of the DMA controller.
13 - clocks: Should contain a clock specifier for each entry in clock-names.
16 - #dma-channels : Number of DMA channels supported. Should be 32.
21 apdma: dma-controller@20100000 {
22 compatible = "sprd,sc9860-dma";
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| /openbmc/linux/Documentation/devicetree/bindings/display/hisilicon/ |
| H A D | hisi-ade.txt | 1 Device-Tree bindings for hisilicon ADE display controller driver
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
15 - clock-names: should contain:
16 "clk_ade_core" for the ADE core clock.
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| /openbmc/linux/Documentation/devicetree/bindings/pwm/ |
| H A D | pwm-hibvt.txt | 4 -compatible: should contain one SoC specific compatible string
6 "hisilicon,hi3516cv300-pwm"
7 "hisilicon,hi3519v100-pwm"
8 "hisilicon,hi3559v100-shub-pwm"
9 "hisilicon,hi3559v100-pwm
10 - reg: physical base address and length of the controller's registers.
11 - clocks: phandle and clock specifier of the PWM reference clock.
12 - resets: phandle and reset specifier for the PWM controller reset.
13 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
18 compatible = "hisilicon,hi3516cv300-pwm";
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