1284aabb0SXinliang LiuDevice-Tree bindings for hisilicon ADE display controller driver 2284aabb0SXinliang Liu 3284aabb0SXinliang LiuADE (Advanced Display Engine) is the display controller which grab image 4284aabb0SXinliang Liudata from memory, do composition, do post image processing, generate RGB 5284aabb0SXinliang Liutiming stream and transfer to DSI. 6284aabb0SXinliang Liu 7284aabb0SXinliang LiuRequired properties: 8284aabb0SXinliang Liu- compatible: value should be "hisilicon,hi6220-ade". 9284aabb0SXinliang Liu- reg: physical base address and length of the ADE controller's registers. 10284aabb0SXinliang Liu- hisilicon,noc-syscon: ADE NOC QoS syscon. 11284aabb0SXinliang Liu- resets: The ADE reset controller node. 12284aabb0SXinliang Liu- interrupt: the ldi vblank interrupt number used. 13284aabb0SXinliang Liu- clocks: a list of phandle + clock-specifier pairs, one for each entry 14284aabb0SXinliang Liu in clock-names. 15284aabb0SXinliang Liu- clock-names: should contain: 16284aabb0SXinliang Liu "clk_ade_core" for the ADE core clock. 17284aabb0SXinliang Liu "clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with 18284aabb0SXinliang Liu jpeg codec. 19*9118c0b7SPeter Meerwald-Stadler "clk_ade_pix" for the ADE pixel clock. 20284aabb0SXinliang Liu- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks' 21284aabb0SXinliang Liu phandle + clock-specifier pairs. 22284aabb0SXinliang Liu- assigned-clock-rates: clock rates, one for each entry in assigned-clocks. 23284aabb0SXinliang Liu The rate of "clk_ade_core" could be "360000000" or "180000000"; 24284aabb0SXinliang Liu The rate of "clk_codec_jpeg" could be or less than "1440000000". 25284aabb0SXinliang Liu These rate values could be configured according to performance and power 26284aabb0SXinliang Liu consumption. 27284aabb0SXinliang Liu- port: the output port. This contains one endpoint subnode, with its 28284aabb0SXinliang Liu remote-endpoint set to the phandle of the connected DSI input endpoint. 29284aabb0SXinliang Liu See Documentation/devicetree/bindings/graph.txt for more device graph info. 30284aabb0SXinliang Liu 31284aabb0SXinliang LiuOptional properties: 32284aabb0SXinliang Liu- dma-coherent: Present if dma operations are coherent. 33284aabb0SXinliang Liu 34284aabb0SXinliang Liu 35284aabb0SXinliang LiuA example of HiKey board hi6220 SoC specific DT entry: 36284aabb0SXinliang LiuExample: 37284aabb0SXinliang Liu 38284aabb0SXinliang Liu ade: ade@f4100000 { 39284aabb0SXinliang Liu compatible = "hisilicon,hi6220-ade"; 40284aabb0SXinliang Liu reg = <0x0 0xf4100000 0x0 0x7800>; 41284aabb0SXinliang Liu reg-names = "ade_base"; 42284aabb0SXinliang Liu hisilicon,noc-syscon = <&medianoc_ade>; 43284aabb0SXinliang Liu resets = <&media_ctrl MEDIA_ADE>; 44284aabb0SXinliang Liu interrupts = <0 115 4>; /* ldi interrupt */ 45284aabb0SXinliang Liu 46284aabb0SXinliang Liu clocks = <&media_ctrl HI6220_ADE_CORE>, 47284aabb0SXinliang Liu <&media_ctrl HI6220_CODEC_JPEG>, 48284aabb0SXinliang Liu <&media_ctrl HI6220_ADE_PIX_SRC>; 49284aabb0SXinliang Liu /*clock name*/ 50284aabb0SXinliang Liu clock-names = "clk_ade_core", 51284aabb0SXinliang Liu "clk_codec_jpeg", 52284aabb0SXinliang Liu "clk_ade_pix"; 53284aabb0SXinliang Liu 54284aabb0SXinliang Liu assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, 55284aabb0SXinliang Liu <&media_ctrl HI6220_CODEC_JPEG>; 56284aabb0SXinliang Liu assigned-clock-rates = <360000000>, <288000000>; 57284aabb0SXinliang Liu dma-coherent; 58284aabb0SXinliang Liu 59284aabb0SXinliang Liu port { 60284aabb0SXinliang Liu ade_out: endpoint { 61284aabb0SXinliang Liu remote-endpoint = <&dsi_in>; 62284aabb0SXinliang Liu }; 63284aabb0SXinliang Liu }; 64284aabb0SXinliang Liu }; 65