1*75219d57SThomas ChouOMAP UART controller 2*75219d57SThomas Chou 3*75219d57SThomas ChouRequired properties: 4*75219d57SThomas Chou- compatible : should be "ti,omap2-uart" for OMAP2 controllers 5*75219d57SThomas Chou- compatible : should be "ti,omap3-uart" for OMAP3 controllers 6*75219d57SThomas Chou- compatible : should be "ti,omap4-uart" for OMAP4 controllers 7*75219d57SThomas Chou- compatible : should be "ti,am4372-uart" for AM437x controllers 8*75219d57SThomas Chou- compatible : should be "ti,am3352-uart" for AM335x controllers 9*75219d57SThomas Chou- compatible : should be "ti,dra742-uart" for DRA7x controllers 10*75219d57SThomas Chou- reg : address and length of the register space 11*75219d57SThomas Chou- interrupts or interrupts-extended : Should contain the uart interrupt 12*75219d57SThomas Chou specifier or both the interrupt 13*75219d57SThomas Chou controller phandle and interrupt 14*75219d57SThomas Chou specifier. 15*75219d57SThomas Chou- ti,hwmods : Must be "uart<n>", n being the instance number (1-based) 16*75219d57SThomas Chou 17*75219d57SThomas ChouOptional properties: 18*75219d57SThomas Chou- clock-frequency : frequency of the clock input to the UART 19*75219d57SThomas Chou- dmas : DMA specifier, consisting of a phandle to the DMA controller 20*75219d57SThomas Chou node and a DMA channel number. 21*75219d57SThomas Chou- dma-names : "rx" for receive channel, "tx" for transmit channel. 22*75219d57SThomas Chou 23*75219d57SThomas ChouExample: 24*75219d57SThomas Chou 25*75219d57SThomas Chou uart4: serial@49042000 { 26*75219d57SThomas Chou compatible = "ti,omap3-uart"; 27*75219d57SThomas Chou reg = <0x49042000 0x400>; 28*75219d57SThomas Chou interrupts = <80>; 29*75219d57SThomas Chou dmas = <&sdma 81 &sdma 82>; 30*75219d57SThomas Chou dma-names = "tx", "rx"; 31*75219d57SThomas Chou ti,hwmods = "uart4"; 32*75219d57SThomas Chou clock-frequency = <48000000>; 33*75219d57SThomas Chou }; 34