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/openbmc/u-boot/drivers/mtd/
H A DKconfig11 flash, RAM and similar chips, often used for solid state file
15 bool "Enable parallel NOR flash support"
17 Enable support for parallel NOR flash.
26 bool "Enable CFI Flash driver"
28 The Common Flash Interface specification was developed by Intel,
29 AMD and other flash manufactures. It provides a universal method
30 for probing the capabilities of flash devices. If you wish to
31 support any device that is CFI-compliant, you need to enable this
32 option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
33 for more information on CFI.
[all …]
H A Dcfi_flash.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2002-2004
33 * This file implements a Common Flash Interface (CFI) driver for
34 * U-Boot.
38 * access CFI data structures.
41 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
42 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
43 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
44 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
45 * AMD CFI Specification, Release 2.0 December 1, 2001
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/openbmc/linux/drivers/mtd/chips/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "RAM/ROM/Flash chip drivers"
6 tristate "Detect flash chips by Common Flash Interface (CFI) probe"
10 The Common Flash Interface specification was developed by Intel,
11 AMD and other flash manufactures that provides a universal method
12 for probing the capabilities of flash devices. If you wish to
13 support any device that is CFI-compliant, you need to enable this
14 option. Visit <https://www.amd.com/products/nvd/overview/cfi.html>
15 for more information on CFI.
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
[all …]
H A Dcfi_cmdset_0002.c1 // SPDX-License-Identifier: GPL-2.0
3 * Common Flash Interface support:
14 * XIP support hooks by Vitaly Wool (based on code for Intel flash
17 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
37 #include <linux/mtd/cfi.h>
52 * Status Register bit description. Used by flash devices that don't
118 * CFI Primary Vendor-Specific Extended Query table 1.5
120 static int cfi_use_status_reg(struct cfi_private *cfi) in cfi_use_status_reg() argument
122 struct cfi_pri_amdstd *extp = cfi->cmdset_priv; in cfi_use_status_reg()
125 return extp && extp->MinorVersion >= '5' && in cfi_use_status_reg()
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H A Dcfi_cmdset_0001.c1 // SPDX-License-Identifier: GPL-2.0
3 * Common Flash Interface support:
10 * - completely revamped method functions so they are aware and
11 * independent of the flash geometry (buswidth, interleave, etc.)
12 * - scalability vs code size is completely set at compile-time
13 * (see include/linux/mtd/cfi.h for selection)
14 * - optimized write buffer method
16 * - reworked lock/unlock/erase support for var size flash
18 * - auto unlock sectors on resume for auto locking flash on power up
37 #include <linux/mtd/cfi.h>
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H A Dcfi_probe.c1 // SPDX-License-Identifier: GPL-2.0
3 Common Flash Interface probe code.
19 #include <linux/mtd/cfi.h>
29 unsigned long *chip_map, struct cfi_private *cfi);
30 static int cfi_chip_setup(struct map_info *map, struct cfi_private *cfi);
46 #define xip_enable(base, map, cfi) \ argument
48 cfi_qry_mode_off(base, map, cfi); \
52 #define xip_disable_qry(base, map, cfi) \ argument
55 cfi_qry_mode_on(base, map, cfi); \
62 #define xip_enable(base, map, cfi) do { } while (0) argument
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H A Dcfi_util.c1 // SPDX-License-Identifier: GPL-2.0
3 * Common Flash Interface support:
23 #include <linux/mtd/cfi.h>
40 struct map_info *map, struct cfi_private *cfi) in cfi_build_cmd_addr() argument
43 unsigned interleave = cfi_interleave(cfi); in cfi_build_cmd_addr()
44 unsigned type = cfi->device_type; in cfi_build_cmd_addr()
62 * Transforms the CFI command for the given geometry (bus width & interleave).
66 map_word cfi_build_cmd(u_long cmd, struct map_info *map, struct cfi_private *cfi) in cfi_build_cmd() argument
85 chip_mode = map_bankwidth(map) / cfi_interleave(cfi); in cfi_build_cmd()
86 chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map); in cfi_build_cmd()
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H A Dgen_probe.c1 // SPDX-License-Identifier: GPL-2.0
3 * Routines common to all CFI-type probes.
4 * (C) 2001-2003 Red Hat, Inc.
12 #include <linux/mtd/cfi.h>
19 struct cfi_private *cfi);
24 struct cfi_private *cfi; in mtd_do_chip_probe() local
26 /* First probe the map to see if we have CFI stuff there. */ in mtd_do_chip_probe()
27 cfi = genprobe_ident_chips(map, cp); in mtd_do_chip_probe()
29 if (!cfi) in mtd_do_chip_probe()
32 map->fldrv_priv = cfi; in mtd_do_chip_probe()
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/openbmc/linux/drivers/mtd/maps/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 bool "Support non-linear mappings of flash chips"
10 paged mappings of flash chips.
13 tristate "Flash device in physical memory map"
16 This provides a 'mapping' driver which allows the NOR Flash and
19 the physical address and size of the flash chips on your
21 with config options or at run-time.
38 hex "Physical start address of flash mapping"
42 This is the physical memory location at which the flash chips
48 hex "Physical length of flash mapping"
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H A Dscb2_flash.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MTD map driver for BIOS Flash on Intel SCB2 boards
20 * * D8-D15 ignored
25 * logical address 0 hit higher-address sections of the chip, not physical 0.
29 * This driver assumes the chip is not write-protected by an external signal.
33 * updates for this board include 10 related (*.bio - &.bi9) binary files and
40 * offset 0x00000 to 0x4ffff (320k): unknown - SCSI BIOS, etc?
54 #include <linux/mtd/cfi.h>
66 .name = "SCB2 BIOS Flash",
76 struct map_info *map = mtd->priv; in scb2_fixup_mtd()
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H A Dsbc_gxx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* sbc_gxx.c -- MTD map driver for Arcom Control Systems SBC-MediaGX,
3 SBC-GXm and SBC-GX1 series boards.
8 The SBC-MediaGX / SBC-GXx has up to 16 MiB of
11 This driver uses the CFI probe and Intel Extended Command Set drivers.
13 The flash is accessed as follows:
15 16 KiB memory window at 0xdc000-0xdffff
20 bit 0-7: address bit 14-21
22 bit 0-1: address bit 22-23
23 bit 7: 0 - reset/powered down
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/openbmc/u-boot/doc/device-tree-bindings/mtd/
H A Dmtd-physmap.txt1 CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
3 Flash chips (Memory Technology Devices) are often used for solid state
6 - compatible : should contain the specific model of mtd chip(s)
7 used, if known, followed by either "cfi-flash", "jedec-flash",
8 "mtd-ram" or "mtd-rom".
9 - reg : Address range(s) of the mtd chip(s)
11 non-identical chips can be described in one node.
12 - bank-width : Width (in bytes) of the bank. Equal to the
14 - device-width : (optional) Width of a single mtd chip. If
15 omitted, assumed to be equal to 'bank-width'.
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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dmtd-physmap.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
10 - Rob Herring <robh@kernel.org>
13 Flash chips (Memory Technology Devices) are often used for solid state
17 - $ref: mtd.yaml#
18 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
23 - items:
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/openbmc/u-boot/arch/mips/mach-bmips/
H A DKconfig135 of RAM and 128 MB of flash (nand).
141 bool "Comtrend AR-5315u"
145 Comtrend AR-5315u boards have a BCM6318 SoC with 64 MB of RAM and 16
146 MB of flash (SPI).
152 bool "Comtrend AR-5387un"
156 Comtrend AR-5387un boards have a BCM6328 SoC with 64 MB of RAM and 16
157 MB of flash (SPI).
163 bool "Comtrend CT-5361"
167 Comtrend CT-5361 boards have a BCM6348 SoC with 16 MB of RAM and 4 MB
168 of flash (CFI).
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/openbmc/u-boot/doc/
H A DREADME.cfi1 The common CFI driver provides this weak default implementation for
9 * that AMD flash roms ignore the Intel command.
18 Some flash chips seem to have trouble with this reset sequence.
19 In this case, board-specific code can override this weak default
20 version with a board-specific function.
38 * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
39 * needs the Spansion type reset commands. The other flash chip
43 if (info->start[0] == CONFIG_SYS_FLASH_BASE)
50 http://www.mail-archive.com/u-boot@lists.denx.de/msg24368.html
55 CONFIG_SYS_MAX_FLASH_SECT: Number of sectors available on Flash device
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/openbmc/qemu/hw/block/
H A Dpflash_cfi01.c2 * CFI parallel flash with Intel command set emulation
24 * - flash read
25 * - flash write
26 * - flash ID read
27 * - sector erase
28 * - CFI queries
31 * It does not support flash interleaving
41 #include "hw/block/flash.h"
42 #include "hw/qdev-properties.h"
43 #include "hw/qdev-properties-system.h"
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H A Dpflash_cfi02.c2 * CFI parallel flash with AMD command set emulation
23 * - flash read
24 * - flash write
25 * - flash ID read
26 * - sector erase
27 * - chip erase
28 * - unlock bypass command
29 * - CFI queries
31 * It does not support flash interleaving.
37 #include "hw/block/flash.h"
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/openbmc/qemu/tests/qtest/
H A Dpflash-cfi02-test.c2 * QTest testcase for parallel flash with AMD command set
7 * See the COPYING file in the top-level directory.
15 * a pflash drive. This enables us to test some flash configurations, but not
16 * all. In particular, we're limited to a 16-bit wide flash device.
20 #define BASE_ADDR (0x100000000ULL - MP_FLASH_SIZE_MAX)
25 /* Use a newtype to keep flash addresses separate from byte addresses. */
90 return (uint64_t)-1; in device_mask()
98 if (c->bank_width == 8) { in bank_mask()
99 return (uint64_t)-1; in bank_mask()
101 return (1ULL << (c->bank_width * 8)) - 1ULL; in bank_mask()
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dfsl,ifc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FSL/NXP Integrated Flash Controller
10 - Li Yang <leoyang.li@nxp.com>
13 NXP's integrated flash controller (IFC) is an advanced version of the
16 external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
21 pattern: "^memory-controller@[0-9a-f]+$"
26 "#address-cells":
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/openbmc/linux/arch/powerpc/boot/dts/
H A Dmedia5200.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
12 &gpt0 { fsl,has-wdt; };
24 stdout-path = &console;
29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
30 bus-frequency = <132000000>; // 132 MHz
31 clock-frequency = <396000000>; // 396 MHz
40 bus-frequency = <132000000>;// 132 MHz
64 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
68 phy-handle = <&phy0>;
72 phy0: ethernet-phy@0 {
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drenesas,rpc-if.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/renesas,rpc-if.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Reduced Pin Count Interface (RPC-IF)
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
13 Renesas RPC-IF allows a SPI flash or HyperFlash connected to the SoC to
16 The flash chip itself should be represented by a subnode of the RPC-IF node.
17 The flash interface is selected based on the "compatible" property of this
19 - if it contains "jedec,spi-nor", then SPI is used;
[all …]
/openbmc/linux/drivers/media/pci/cobalt/
H A Dcobalt-flash.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cobalt NOR flash functions
5 * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
11 #include <linux/mtd/cfi.h>
14 #include "cobalt-flash.h"
19 .name = "cobalt-flash",
29 r.x[0] = cobalt_bus_read32(map->virt, ADRS(offset)); in flash_read16()
43 cobalt_bus_write16(map->virt, ADRS(offset), data); in flash_write16()
54 data = cobalt_bus_read32(map->virt, ADRS(src)); in flash_copy_from()
59 len--; in flash_copy_from()
[all …]
/openbmc/u-boot/include/configs/
H A Dvct.h1 /* SPDX-License-Identifier: GPL-2.0+ */
52 #define CONFIG_SYS_NS16550_REG_SIZE -4
81 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
96 * FLASH and environment organization
102 * We need special accessor functions for the CFI FLASH driver. This
108 * For the non-memory-mapped NOR FLASH, we need to define the
109 * NOR FLASH area. This can't be detected via the addr2info()
110 * function, since we check for flash access in the very early
111 * U-Boot code, before the NOR FLASH is detected.
117 * CFI driver settings
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dgef_ppc9a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe8000000 0x08000000 // Paged Flash 0
33 2 0 0xe0000000 0x08000000 // Paged Flash 1
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
40 /* flash@0,0 is a mirror of part of the memory in flash@1,0
41 flash@0,0 {
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H A Dgef_sbc610.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
17 /include/ "mpc8641si-pre.dtsi"
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe8000000 0x08000000 // Paged Flash 0
33 2 0 0xe0000000 0x08000000 // Paged Flash 1
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
40 /* flash@0,0 is a mirror of part of the memory in flash@1,0
41 flash@0,0 {
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