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/openbmc/linux/drivers/net/can/sja1000/
H A Dsja1000_isa.c1 // SPDX-License-Identifier: GPL-2.0-only
24 MODULE_DESCRIPTION("Socket-CAN driver for SJA1000 on the ISA bus");
35 static unsigned char cdr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff}; variable
36 static unsigned char ocr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff};
37 static int indirect[MAXDEV] = {[0 ... (MAXDEV - 1)] = -1};
38 static spinlock_t indirect_lock[MAXDEV]; /* lock for indirect access mode */
56 module_param_array(cdr, byte, NULL, 0444);
57 MODULE_PARM_DESC(cdr, "Clock divider register "
71 return readb(priv->reg_base + reg); in sja1000_isa_mem_read_reg()
77 writeb(val, priv->reg_base + reg); in sja1000_isa_mem_write_reg()
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H A Dsja1000_platform.c1 // SPDX-License-Identifier: GPL-2.0-only
28 MODULE_DESCRIPTION("Socket-CAN driver for SJA1000 on the platform bus");
43 return ioread8(priv->reg_base + reg); in sp_read_reg8()
48 iowrite8(val, priv->reg_base + reg); in sp_write_reg8()
53 return ioread8(priv->reg_base + reg * 2); in sp_read_reg16()
58 iowrite8(val, priv->reg_base + reg * 2); in sp_write_reg16()
63 return ioread8(priv->reg_base + reg * 4); in sp_read_reg32()
68 iowrite8(val, priv->reg_base + reg * 4); in sp_write_reg32()
73 struct technologic_priv *tp = priv->priv; in sp_technologic_read_reg16()
77 spin_lock_irqsave(&tp->io_lock, flags); in sp_technologic_read_reg16()
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H A Dplx_pci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
7 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
8 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
26 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
37 /* Pointer to device-dependent reset function */
71 * This means normal output mode, push-pull and the correct polarity.
79 * In the CDR register, you should set CBP to 1.
86 /* SJA1000 Control Register in the BasicCAN Mode */
89 /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
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H A Dems_pcmcia.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2010 Markus Plessing <plessing@ems-wuensche.com>
22 MODULE_AUTHOR("Markus Plessing <plessing@ems-wuensche.com>");
23 MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-CARD cards");
43 * This means normal output mode , push-pull and the correct polarity.
48 * In the CDR register, you should set CBP to 1.
54 #define EMS_PCMCIA_MEM_SIZE 4096 /* Size of the remapped io-memory */
63 PCMCIA_DEVICE_PROD_ID123("EMS_T_W", "CPC-Card", "V2.0", 0xeab1ea23,
72 return readb(priv->reg_base + port); in ems_pcmcia_read_reg()
78 writeb(val, priv->reg_base + port); in ems_pcmcia_write_reg()
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H A Dkvaser_pci.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * - Kvaser linux driver, version 4.72 BETA
8 * Copyright (C) 2002-2007 KVASER AB
10 * - Lincan driver, version 0.3.3, OCERA project
14 * - Socketcan SJA1000 drivers
16 * Copyright (c) 2002-2007 Volkswagen Group Electronic Research
35 MODULE_DESCRIPTION("Socket-CAN driver for KVASER PCAN PCI cards");
43 struct net_device *slave_dev[MAX_NO_OF_CHANNELS-1];
58 * This means normal output mode , push-pull and the correct polarity.
63 * In the CDR register, you should set CBP to 1.
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H A Dpeak_pcmcia.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2010-2012 Stephane Grosjean <s.grosjean@peak-system.com>
5 * CAN driver for PEAK-System PCAN-PC Card
7 * Copyright (C) 2006-2010 PEAK System-Technik GmbH
22 MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>");
23 MODULE_DESCRIPTION("CAN driver for PEAK-System PCAN-PC Cards");
26 /* PEAK-System PCMCIA driver name */
117 * This means normal output mode, push-pull and the correct polarity.
122 * In the CDR register, you should set CBP to 1.
135 /* PCAN-PC Card private structure */
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H A Dems_pci.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
5 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
23 MODULE_AUTHOR("Sebastian Haas <support@ems-wuensche.com>");
24 MODULE_AUTHOR("Gerhard Uttenthaler <uttenthaler@ems-wuensche.com>");
25 MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
48 * PSB4610 PITA-2 bridge control registers
80 * This means normal output mode, push-pull and the correct polarity.
84 /* In the CDR register, you should set CBP to 1.
114 /* CPC-PCI v1 */
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H A Dsja1000.h2 * sja1000.h - Philips SJA1000 network device driver
7 * Copyright (c) 2002-2007 Volkswagen Group Electronic Research
56 /* SJA1000 registers - manual section 6.4 (Pelican Mode) */
78 /* Common registers - manual section 6.5 */
98 /* mode register */
159 /* the lower-layer is responsible for appropriate locking */
165 void *priv; /* for board-specific data */
172 u16 flags; /* custom mode flags */
174 u8 cdr; /* clock divider register */ member
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Damd-xgbe.txt1 * AMD 10GbE driver (amd-xgbe)
4 - compatible: Should be "amd,xgbe-seattle-v1a"
5 - reg: Address and length of the register sets for the device
6 - MAC registers
7 - PCS registers
8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
11 - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
13 amd,per-channel-interrupt property is specified, then one additional
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H A Dcortina.txt2 ---------------------------------------
7 devices, equipped with clock and data recovery (CDR) circuits. These
10 "ethernet-phy-id" compatible.
12 Since the driver only implements polling mode support, interrupts info
18 compatible = "ethernet-phy-id13e5.1002";
/openbmc/u-boot/arch/m68k/cpu/mcf532x/
H A Dspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2000-2003
7 * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
56 /* Test to see if device is in LIMP mode */ in get_sys_clock()
57 if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) { in get_sys_clock()
58 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); in get_sys_clock()
67 u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; in get_sys_clock()
68 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); in get_sys_clock()
69 u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1; in get_sys_clock()
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/openbmc/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-xgbe-b.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <250000000>;
12 clock-output-names = "xgmacclk0_dma_250mhz";
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <250000000>;
19 clock-output-names = "xgmacclk0_ptp_250mhz";
23 compatible = "fixed-clock";
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/openbmc/u-boot/include/
H A Dsja1000.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * SJA1000 register layout for basic CAN mode
12 * SJA1000 register layout in basic can mode
27 u8 cdr; member
/openbmc/linux/include/linux/can/platform/
H A Dsja1000.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define CDR_PELICAN 0x80 /* PeliCAN mode */
33 u8 cdr; /* clock divider register */ member
/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dti,ds90ub960.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments DS90UB9XX Family FPD-Link Deserializer Hubs
10 - Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
13 The TI DS90UB9XX devices are FPD-Link video deserializers with I2C and GPIO
17 - $ref: /schemas/i2c/i2c-atr.yaml#
22 - ti,ds90ub960-q1
23 - ti,ds90ub9702-q1
33 clock-names:
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/openbmc/u-boot/arch/arm/dts/
H A Dexynos5420-peach-pit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * SAMSUNG/GOOGLE Peach-Pit board device tree source
9 /dts-v1/;
11 #include <dt-bindings/clock/maxim,max77802.h>
12 #include <dt-bindings/regulator/maxim,max77802.h>
17 compatible = "google,pit-rev#", "google,pit",
21 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
22 hwid = "PIT TEST A-A 7848";
23 lazy-init = <1>;
34 compatible = "pwm-backlight";
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H A Dexynos5250-spring.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/input/input.h>
48 samsung,bl1-offset = <0x1400>;
49 samsung,bl2-offset = <0x3400>;
50 u-boot-memory = "/memory";
51 u-boot-offset = <0x3e00000 0x100000>;
56 #address-cells = <1>;
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/openbmc/u-boot/drivers/misc/
H A Dmpc83xx_serdes.h1 /* SPDX-License-Identifier: GPL-2.0+ */
8 * enum srdscr0_mask - Bit masks for SRDSCR0 (SerDes Control Register 0)
9 * @SRDSCR0_DPPA: Bitmask for the DPPA (diff pk-pk swing for lane A)
11 * @SRDSCR0_DPPE: Bitmask for the DPPE (diff pk-pk swing for lane E)
13 * @SRDSCR0_DPP_1V2: Combined bitmask to set diff pk-pk swing for both lanes
22 SRDSCR0_DPPA = BIT(31 - 16),
23 SRDSCR0_DPPE = BIT(31 - 20),
33 * enum srdscr1_mask - Bit masks for SRDSCR1 (SerDes Control Register 1)
37 SRDSCR1_PLLBW = BIT(31 - 25),
41 * enum srdscr2_mask - Bit masks for SRDSCR2 (SerDes Control Register 2)
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/openbmc/linux/drivers/mtd/devices/
H A Ddocg3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Handles the M-Systems DiskOnChip G3 chip
32 * As no specification is available from M-Systems/Sandisk, this drivers lacks
34 * - IPL write
40 * - a 1 byte Hamming code stored in the OOB for each page
41 * - a 7 bytes BCH code stored in the OOB for each page
43 * - BCH is in GF(2^14)
44 * - BCH is over data of 520 bytes (512 page + 7 page_info bytes
46 * - BCH can correct up to 4 bits (t = 4)
47 * - BCH syndroms are calculated in hardware, and checked in hardware as well
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf5227x/
H A Dspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
44 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); in clock_enter_limp()
46 /* Enable Limp Mode */ in clock_enter_limp()
47 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_enter_limp()
51 * brief Exit Limp mode
52 * warning The PLL should be set and locked prior to exiting Limp mode
59 /* Exit Limp mode */ in clock_exit_limp()
60 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_exit_limp()
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/openbmc/linux/drivers/scsi/mvsas/
H A Dmv_defs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
44 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
79 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
93 MODE_SAS_PORT7_MASK = (1U << 7), /* port0 SAS(1), SATA(0) mode */
135 /* shl for ports 1-3 */
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H A Dmv_64xx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
17 /* enhanced mode registers (BAR4) */
53 /* ports 1-3 follow after this */
56 /* ports 5-7 follow after this */
60 /* ports 1-3 follow after this */
62 /* ports 5-7 follow after this */
68 /* ports 1-3 follow after this */
71 /* ports 5-7 follow after this */
75 /* ports 1-3 follow after this */
[all …]
/openbmc/linux/include/linux/bcma/
H A Dbcma_driver_pci.h1 /* SPDX-License-Identifier: GPL-2.0 */
113 #define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */
162 #define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */
163 #define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */
205 /* PCIE Root Capability Register bits (Host mode only) */
237 #define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)
238 #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
239 #define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)
240 #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
256 return -ENOTSUPP; in bcma_core_pci_pcibios_map_irq()
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/openbmc/linux/drivers/spi/
H A Dspi-sun4i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012 - 2014 Allwinner Tech
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
92 return readl(sspi->base_addr + reg); in sun4i_spi_read()
97 writel(value, sspi->base_addr + reg); in sun4i_spi_write()
138 while (len--) { in sun4i_spi_drain_fifo()
139 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG); in sun4i_spi_drain_fifo()
140 if (sspi->rx_buf) in sun4i_spi_drain_fifo()
141 *sspi->rx_buf++ = byte; in sun4i_spi_drain_fifo()
151 cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi); in sun4i_spi_fill_fifo()
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/openbmc/u-boot/drivers/spi/
H A Dspi-sunxi.c10 * linux/drivers/spi/spi-sun4i.c
12 * Copyright (C) 2012 - 2014 Allwinner Tech
16 * Maxime Ripard <maxime.ripard@free-electrons.com>
18 * SPDX-License-Identifier: GPL-2.0+
77 #define SPI_REG(priv, reg) ((priv)->base + \
78 (priv)->variant->regs[reg])
79 #define SPI_BIT(priv, bit) ((priv)->variant->bits[bit])
134 u32 mode; member
144 while (len--) { in sun4i_spi_drain_fifo()
146 if (priv->rx_buf) in sun4i_spi_drain_fifo()
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