Lines Matching +full:cdr +full:- +full:mode

1 /* SPDX-License-Identifier: GPL-2.0+ */
8  * enum srdscr0_mask - Bit masks for SRDSCR0 (SerDes Control Register 0)
9  * @SRDSCR0_DPPA:       Bitmask for the DPPA (diff pk-pk swing for lane A)
11  * @SRDSCR0_DPPE:       Bitmask for the DPPE (diff pk-pk swing for lane E)
13  * @SRDSCR0_DPP_1V2:    Combined bitmask to set diff pk-pk swing for both lanes
22 	SRDSCR0_DPPA        = BIT(31 - 16),
23 	SRDSCR0_DPPE        = BIT(31 - 20),
33  * enum srdscr1_mask - Bit masks for SRDSCR1 (SerDes Control Register 1)
37 	SRDSCR1_PLLBW = BIT(31 - 25),
41  * enum srdscr2_mask - Bit masks for SRDSCR2 (SerDes Control Register 2)
89  * enum srdscr3_mask - Bit masks for SRDSCR3 (SerDes Control Register 3)
115  * KFRA = 'Kfr' gain selection in the CDR for lane A
116  * KFRE = 'Kfr' gain selection in the CDR for lane E
141  * enum srdscr4_mask - Bit masks for SRDSCR4 (SerDes Control Register 4)
193  * enum srdsrstctl_mask - Bit masks for SRDSRSTCTL (SerDes Reset Control Register)
205  * struct mpc83xx_serdes_regs - Register map of the SerDes controller
225  * enum pex_type - Types of PCI Express
226  * @PEX_X1: PCI Express in x1 mode
227  * @PEX_X2: PCI Express in x2 mode