1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2067f54c6SMatthias Fuchs /* 3067f54c6SMatthias Fuchs * Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu> 4067f54c6SMatthias Fuchs * 5067f54c6SMatthias Fuchs * SJA1000 register layout for basic CAN mode 6067f54c6SMatthias Fuchs */ 7067f54c6SMatthias Fuchs 8067f54c6SMatthias Fuchs #ifndef _SJA1000_H_ 9067f54c6SMatthias Fuchs #define _SJA1000_H_ 10067f54c6SMatthias Fuchs 11067f54c6SMatthias Fuchs /* 12067f54c6SMatthias Fuchs * SJA1000 register layout in basic can mode 13067f54c6SMatthias Fuchs */ 14067f54c6SMatthias Fuchs struct sja1000_basic_s { 15067f54c6SMatthias Fuchs u8 cr; 16067f54c6SMatthias Fuchs u8 cmr; 17067f54c6SMatthias Fuchs u8 sr; 18067f54c6SMatthias Fuchs u8 ir; 19067f54c6SMatthias Fuchs u8 ac; 20067f54c6SMatthias Fuchs u8 am; 21067f54c6SMatthias Fuchs u8 btr0; 22067f54c6SMatthias Fuchs u8 btr1; 23067f54c6SMatthias Fuchs u8 oc; 24067f54c6SMatthias Fuchs u8 txb[10]; 25067f54c6SMatthias Fuchs u8 rxb[10]; 26067f54c6SMatthias Fuchs u8 unused; 27067f54c6SMatthias Fuchs u8 cdr; 28067f54c6SMatthias Fuchs }; 29067f54c6SMatthias Fuchs 30067f54c6SMatthias Fuchs /* control register */ 31067f54c6SMatthias Fuchs #define CR_RR 0x01 32067f54c6SMatthias Fuchs 33067f54c6SMatthias Fuchs /* output control register */ 34067f54c6SMatthias Fuchs #define OC_MODE0 0x01 35067f54c6SMatthias Fuchs #define OC_MODE1 0x02 36067f54c6SMatthias Fuchs #define OC_POL0 0x04 37067f54c6SMatthias Fuchs #define OC_TN0 0x08 38067f54c6SMatthias Fuchs #define OC_TP0 0x10 39067f54c6SMatthias Fuchs #define OC_POL1 0x20 40067f54c6SMatthias Fuchs #define OC_TN1 0x40 41067f54c6SMatthias Fuchs #define OC_TP1 0x80 42067f54c6SMatthias Fuchs 43067f54c6SMatthias Fuchs #endif 44