| /openbmc/linux/drivers/clk/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
14 select HAVE_CLK
16 Select this option when the clock API in <linux/clk.h> is implemented
18 code should select COMMON_CLK instead and not define a custom
22 bool "Common Clock Framework"
24 select HAVE_CLK_PREPARE
25 select HAVE_CLK
26 select RATIONAL
28 The common clock framework is a single definition of struct
[all …]
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| /openbmc/linux/drivers/rtc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
11 select RTC_LIB
14 bool "Real Time Clock"
17 select RTC_LIB
29 If you say yes here, the system time (wall clock) will be set using
39 clock, usually rtc0. Initialization is done when the system
44 This clock should be battery-backed, so that it reads the correct
45 time when the system boots from a power-off state. Otherwise, your
46 system will need an external clock source (like an NTP server).
48 If the clock you specify here is not battery backed, it may still
[all …]
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| /openbmc/linux/Documentation/arch/m68k/ |
| H A D | buddha-driver.rst | 8 ------------------------------------------------------------------------
11 Buddha-part of the Catweasel Zorro-II version
21 product number: 0 (42 for Catweasel Z-II)
23 Rom-vector: $1000
25 The card should be a Z-II board, size 64K, not for freemem
26 list, Rom-Vektor is valid, no second Autoconfig-board on the
30 as the Amiga Kickstart does: The lower nibble of the 8-Bit
36 otherwise your chance is only 1:16 to find the board :-).
38 The local memory-map is even active when mapped to $e8:
41 $0-$7e Autokonfig-space, see Z-II docs.
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | ti-aemif.txt | 4 provide a glue-less interface to a variety of asynchronous memory devices like
6 can be accessed at any given time via four chip selects with 64M byte access
7 per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
[all …]
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| H A D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
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| H A D | arm,pl35x-smc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 The PL35x Static Memory Controller is a bus where you can connect two kinds
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
20 # We need a select here so we don't match all nodes with 'arm,primecell'
21 select:
26 - arm,pl353-smc-r2p1
[all …]
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| /openbmc/u-boot/drivers/clk/at91/ |
| H A D | Kconfig | 2 bool "AT91 clock drivers"
4 select MISC
6 This option is used to enable the AT91 clock driver.
7 The driver supports the AT91 clock generator, including
8 the oscillators and PLLs, such as main clock, slow clock,
9 PLLA, UTMI PLL. Clocks can also be a source clock of other
10 clocks a tree structure, such as master clock, usb device
11 clock, matrix clock and generic clock.
12 Devices can use a common clock API to request a particular
13 clock, enable it and get its rate.
[all …]
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| /openbmc/linux/drivers/clk/baikal-t1/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Baikal-T1 Clocks Control Unit interface"
7 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
9 consists of multiple global clock domains, which can be reset by
12 configurable and fixed clock dividers. Enable this option to be able
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
18 bool "Baikal-T1 CCU PLLs support"
19 select MFD_SYSCON
22 Enable this to support the PLLs embedded into the Baikal-T1 SoC
27 CPUs, DDR, etc.) or passed over the clock dividers to be only
[all …]
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | Kconfig | 3 select ARMV8_SET_SMPEN
4 select ARM_ERRATA_855873 if !TFABOOT
5 select FSL_LAYERSCAPE
6 select FSL_LSCH2
7 select SYS_FSL_SRDS_1
8 select SYS_HAS_SERDES
9 select SYS_FSL_DDR_BE
10 select SYS_FSL_MMDC
11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | micrel.txt | 7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
32 actually select a mode.
34 - clocks, clock-names: contains clocks according to the common clock bindings.
37 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
38 input clock. Used to determine the XI input clock.
[all …]
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| /openbmc/u-boot/drivers/serial/ |
| H A D | Kconfig | 11 Select a default baudrate, where "default" has a driver-specific
19 # non-dm serial code
34 in U-Boot.
41 In very space-constrained devices even the full UART driver is too
42 large. In this case the debug UART can still be used in some cases.
43 This option enables the full UART in U-Boot, so if is it disabled,
51 In very space-constrained devices even the full UART driver is too
52 large. In this case the debug UART can still be used in some cases.
61 In very space-constrained devices even the full UART driver is too
62 large. In this case the debug UART can still be used in some cases.
[all …]
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| /openbmc/linux/drivers/ptp/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # PTP clock support configuration
6 menu "PTP clock support"
9 tristate "PTP clock support"
12 select PPS
13 select NET_PTP_CLASSIFY
17 standard defines a Precision Time Protocol (PTP), which can
20 time stamping units, it can be possible to achieve
24 devices. If you want to use a PTP clock, then you should
25 also enable at least one clock driver as well.
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/bus/ |
| H A D | nvidia,tegra20-gmi.txt | 4 external memory. Can be used to attach various high speed devices such as
10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ti/ |
| H A D | dra7-atl.txt | 1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
9 In order to provide the support for ATL and its output clocks (which can be used
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
[all …]
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| /openbmc/linux/arch/m68k/ |
| H A D | Kconfig.cpu | 1 # SPDX-License-Identifier: GPL-2.0
13 applications, and are all System-On-Chip (SOC) devices, as opposed
17 MC68xxx processor, select M68KCLASSIC.
19 processor, select COLDFIRE.
23 select HAVE_ARCH_PFN_VALID
27 select CPU_HAS_NO_BITFIELDS
28 select CPU_HAS_NO_CAS
29 select CPU_HAS_NO_MULDIV64
30 select GENERIC_CSUM
31 select GPIOLIB
[all …]
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| /openbmc/linux/drivers/net/ethernet/freescale/enetc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
8 If compiled as module (M), the module name is fsl-enetc-core.
13 select MDIO_DEVRES
14 select FSL_ENETC_CORE
15 select FSL_ENETC_IERB
16 select FSL_ENETC_MDIO
17 select PHYLINK
18 select PCS_LYNX
19 select DIMLIB
25 If compiled as module (M), the module name is fsl-enetc.
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | adi,ad7124.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Stefan Popa <stefan.popa@analog.com>
14 Bindings for the Analog Devices AD7124 ADC device. Datasheet can be
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7124-8.pdf
21 - adi,ad7124-4
22 - adi,ad7124-8
25 description: SPI chip select number for the device
30 description: phandle to the master clock (mclk)
[all …]
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| H A D | adi,ad4130.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Cosmin Tanislav <cosmin.tanislav@analog.com>
14 Bindings for the Analog Devices AD4130 ADC. Datasheet can be found here:
15 https://www.analog.com/media/en/technical-documentation/data-sheets/AD4130-8.pdf
20 - adi,ad4130
27 description: phandle to the master clock (mclk)
29 clock-names:
31 - const: mclk
[all …]
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| /openbmc/linux/drivers/devfreq/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 select PM_OPP
7 devfreq, a generic DVFS framework can be registered for a device
11 Each device may have its own governor and policy. Devfreq can
16 However, because the clock frequencies of a single device are
19 clock frequency of the device, which is also attached
20 to a device by 1-to-1. The device registering devfreq takes the
22 to set its every clock accordingly with the "target" callback
39 Simple-Ondemand should be able to provide busy/total counter
81 select DEVFREQ_GOV_SIMPLE_ONDEMAND
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/net/can/ |
| H A D | renesas,rcar-can.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/renesas,rcar-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car CAN Controller
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,can-r8a7778 # R-Car M1-A
18 - renesas,can-r8a7779 # R-Car H1
[all …]
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | Kconfig | 4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
65 Support for the PRCM (Power/Reset/Clock Management) unit available
71 Select this PMIC bus access helpers for Sunxi platform PRCM or other
[all …]
|
| /openbmc/linux/arch/sh/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 select ARCH_32BIT_OFF_T
5 select ARCH_ENABLE_MEMORY_HOTPLUG if SPARSEMEM && MMU
6 select ARCH_ENABLE_MEMORY_HOTREMOVE if SPARSEMEM && MMU
7 select ARCH_HAVE_NMI_SAFE_CMPXCHG if (GUSA_RB || CPU_SH4A)
8 select ARCH_HAS_BINFMT_FLAT if !MMU
9 select ARCH_HAS_CPU_FINALIZE_INIT
10 select ARCH_HAS_CURRENT_STACK_POINTER
11 select ARCH_HAS_GIGANTIC_PAGE
12 select ARCH_HAS_GCOV_PROFILE_ALL
[all …]
|
| /openbmc/u-boot/doc/ |
| H A D | README.fsl-hwconfig | 1 Freescale-specific 'hwconfig' options.
3 This file documents Freescale-specific key:value pairs for the 'hwconfig'
10 routed to the Wolfson WM8776 codec. The ngPIXIS can be programmed to
11 route either a 11.2896MHz or a 12.288MHz clock. The default is
13 will be programmed accordingly. Second, the clock-frequency property
18 Select the 11.2896MHz clock
21 Select the 12.288MHz clock
28 - which controller mode to use
29 - which USB PHY to use
31 This is used by generic USB device-tree fixup function to update
[all …]
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| /openbmc/u-boot/doc/device-tree-bindings/spi/ |
| H A D | spi-bus.txt | 3 SPI busses can be described with a node for the SPI master device
10 - #address-cells - number of cells required to define a chip select
12 - #size-cells - should be zero.
13 - compatible - name of SPI bus controller following generic names
15 - cs-gpios - (optional) gpios chip select.
19 assigning chip select numbers. Since SPI chip select configuration is
20 flexible and non-standardized, it is left out of this binding with the
22 chip selects. Individual drivers can define additional properties to
23 support describing the chip select layout.
26 - num-cs : total number of chipselects
[all …]
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| /openbmc/u-boot/drivers/clk/ |
| H A D | Kconfig | 1 menu "Clock" menu
4 bool "Enable clock driver support"
7 This allows drivers to be provided for clock generators, including
8 oscillators and PLLs. Devices can use a common clock API to request
9 a particular clock rate and check on available clocks. Clocks can
11 choose the source for each clock.
14 bool "Enable clock support in SPL"
17 The clock subsystem adds a small amount of overhead to the image.
18 If this is acceptable and you have a need to use clock drivers in
21 used as U-Boot proper.
[all …]
|