arch/m68k/Kconfig.cpu

1 # SPDX-License-Identifier: GPL-2.0
13 	  applications, and are all System-On-Chip (SOC) devices, as opposed
17 	  MC68xxx processor, select M68KCLASSIC.
19 	  processor, select COLDFIRE.
23 	select HAVE_ARCH_PFN_VALID
27 	select CPU_HAS_NO_BITFIELDS
28 	select CPU_HAS_NO_CAS
29 	select CPU_HAS_NO_MULDIV64
30 	select GENERIC_CSUM
31 	select GPIOLIB
32 	select HAVE_LEGACY_CLK
41 	select CPU_HAS_NO_BITFIELDS
42 	select CPU_HAS_NO_CAS
43 	select CPU_HAS_NO_MULDIV64
44 	select CPU_HAS_NO_UNALIGNED
45 	select GENERIC_CSUM
46 	select CPU_NO_EFFICIENT_FFS
47 	select HAVE_ARCH_HASH
48 	select LEGACY_TIMER_TICK
53 	  System-On-Chip devices (eg 68328, 68302, etc). It does not contain
59 	select FPU
60 	select CPU_HAS_ADDRESS_SPACES
70 	select FPU
71 	select CPU_HAS_ADDRESS_SPACES
80 	select FPU
81 	select CPU_HAS_ADDRESS_SPACES
91 	select FPU
92 	select CPU_HAS_ADDRESS_SPACES
100 	select M68000
107 	select M68000
114 	select M68000
126 	  Select the type of ColdFire System-on-Chip (SoC) that you want
132 	select COLDFIRE_SW_A7
133 	select COLDFIRE_TIMERS
134 	select HAVE_MBAR
135 	select CPU_NO_EFFICIENT_FFS
142 	select COLDFIRE_SW_A7
143 	select COLDFIRE_TIMERS
144 	select HAVE_MBAR
145 	select CPU_NO_EFFICIENT_FFS
152 	select COLDFIRE_PIT_TIMER
153 	select HAVE_CACHE_SPLIT
160 	select COLDFIRE_PIT_TIMER
161 	select HAVE_CACHE_SPLIT
162 	select HAVE_IPSBAR
169 	select COLDFIRE_SW_A7
170 	select COLDFIRE_TIMERS
171 	select HAVE_MBAR
172 	select CPU_NO_EFFICIENT_FFS
179 	select COLDFIRE_SW_A7
180 	select COLDFIRE_TIMERS
181 	select HAVE_MBAR
182 	select CPU_NO_EFFICIENT_FFS
189 	select COLDFIRE_PIT_TIMER
190 	select M527x
191 	select HAVE_CACHE_SPLIT
192 	select HAVE_IPSBAR
199 	select COLDFIRE_SW_A7
200 	select COLDFIRE_TIMERS
201 	select HAVE_MBAR
202 	select CPU_NO_EFFICIENT_FFS
209 	select COLDFIRE_PIT_TIMER
210 	select M527x
211 	select HAVE_CACHE_SPLIT
212 	select HAVE_IPSBAR
219 	select COLDFIRE_PIT_TIMER
220 	select HAVE_CACHE_SPLIT
221 	select HAVE_IPSBAR
228 	select COLDFIRE_TIMERS
229 	select COLDFIRE_SW_A7
230 	select HAVE_CACHE_CB
231 	select HAVE_MBAR
232 	select CPU_NO_EFFICIENT_FFS
239 	select COLDFIRE_TIMERS
240 	select M53xx
241 	select HAVE_CACHE_CB
248 	select COLDFIRE_TIMERS
249 	select M53xx
250 	select HAVE_CACHE_CB
257 	select COLDFIRE_SW_A7
258 	select COLDFIRE_TIMERS
259 	select HAVE_CACHE_CB
260 	select HAVE_MBAR
261 	select CPU_NO_EFFICIENT_FFS
267 	select M54xx
268 	select COLDFIRE_SLTIMERS
269 	select MMU_COLDFIRE if MMU
270 	select FPU if MMU
271 	select HAVE_CACHE_CB
272 	select HAVE_MBAR
273 	select CPU_NO_EFFICIENT_FFS
279 	select COLDFIRE_SLTIMERS
280 	select MMU_COLDFIRE if MMU
281 	select FPU if MMU
282 	select M54xx
283 	select HAVE_CACHE_CB
284 	select HAVE_MBAR
285 	select CPU_NO_EFFICIENT_FFS
291 	select COLDFIRE_PIT_TIMER
292 	select MMU_COLDFIRE if MMU
293 	select HAVE_CACHE_CB
306 	select HAVE_PCI
314 	select LEGACY_TIMER_TICK
318 	select LEGACY_TIMER_TICK
328 	  At some point in the future, this will cause floating-point math
330 	  floating-point math coprocessor.  Thrill-seekers and chronically
331 	  sleep-deprived psychotic hacker types can say Y now, everyone else
339 	  correct rounding, the emulator can (often) do the same but this
340 	  extra calculation can cost quite some time, so you can disable
349 	  This option prevents any floating-point instructions from being
352 	  kernel will only be usable on machines without a floating-point
354 	  needs to be executed whether a floating-point instruction in the
373 	bool "Use read-modify-write instructions"
377 	  read-modify-write bus cycles. While this is faster than the
378 	  workaround of disabling interrupts, it can conflict with DMA
382 	  configuration where it should work are 68030-based Ataris, where it
406 	  defines the maximal power of two of number of pages that can be
418 	bool "Use write-through caching for 68060 supervisor accesses"
422 	  Copyback caching means that memory writes will be held in an on-chip
451 	select ALTERNATE_USER_ADDRESS_SPACE
472 	int "Set the core clock frequency"
484 	  Define the CPU clock frequency in use. This is the core clock
485 	  frequency, it may or may not be the same as the external clock
487 	  PLL and can have their frequency programmed at run time, others
528 	bool "Write-through"
530 	  The ColdFire CPU cache is set into Write-through mode.
533 	bool "Copy-back"
535 	  The ColdFire CPU cache is set into Copy-back mode.