Lines Matching +full:can +full:- +full:clock +full:- +full:select
4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
65 Support for the PRCM (Power/Reset/Clock Management) unit available
71 Select this PMIC bus access helpers for Sunxi platform PRCM or other
87 ---help---
100 ---help---
101 Select this for sunxi SoCs which have resets and clocks set up
102 as the original A10 (mach-sun4i).
106 ---help---
107 Select this for sunxi SoCs which have sun6i like periphery, like
113 ---help---
114 Select this for sunxi SoCs which uses a DRAM controller like the
116 not have official open-source DRAM initialization code, but can
122 ---help---
123 Select this for sunxi SoCs with DesignWare DRAM controller and
124 have only 16-bit memory buswidth.
128 ---help---
129 Select this for sunxi SoCs with DesignWare DRAM controller with
130 32-bit memory buswidth.
135 select DM_I2C
136 select PHY_SUN4I_USB
137 select SUNXI_DE2
138 select SUNXI_DRAM_DW
139 select SUNXI_DRAM_DW_32BIT
140 select SUNXI_GEN_SUN6I
141 select SUPPORT_SPL
155 select CPU_V7A
156 select ARM_CORTEX_CPU_IS_UP
157 select DM_MMC if MMC
158 select DM_SCSI if SCSI
159 select PHY_SUN4I_USB
160 select DRAM_SUN4I
161 select SUNXI_GEN_SUN4I
162 select SUPPORT_SPL
166 select CPU_V7A
167 select ARM_CORTEX_CPU_IS_UP
168 select DM_MMC if MMC
169 select DRAM_SUN4I
170 select PHY_SUN4I_USB
171 select SUNXI_GEN_SUN4I
172 select SUPPORT_SPL
177 select CPU_V7A
178 select CPU_V7_HAS_NONSEC
179 select CPU_V7_HAS_VIRT
180 select ARCH_SUPPORT_PSCI
181 select DM_MMC if MMC
182 select DRAM_SUN6I
183 select PHY_SUN4I_USB
184 select SUN6I_P2WI
185 select SUN6I_PRCM
186 select SUNXI_GEN_SUN6I
187 select SUPPORT_SPL
188 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
192 select CPU_V7A
193 select CPU_V7_HAS_NONSEC
194 select CPU_V7_HAS_VIRT
195 select ARCH_SUPPORT_PSCI
196 select DRAM_SUN4I
197 select PHY_SUN4I_USB
198 select SUNXI_GEN_SUN4I
199 select SUPPORT_SPL
200 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
204 select CPU_V7A
205 select CPU_V7_HAS_NONSEC
206 select CPU_V7_HAS_VIRT
207 select ARCH_SUPPORT_PSCI
208 select DM_MMC if MMC
209 select DRAM_SUN8I_A23
210 select PHY_SUN4I_USB
211 select SUNXI_GEN_SUN6I
212 select SUPPORT_SPL
213 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
218 select CPU_V7A
219 select CPU_V7_HAS_NONSEC
220 select CPU_V7_HAS_VIRT
221 select ARCH_SUPPORT_PSCI
222 select DM_MMC if MMC
223 select DRAM_SUN8I_A33
224 select PHY_SUN4I_USB
225 select SUNXI_GEN_SUN6I
226 select SUPPORT_SPL
227 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
232 select CPU_V7A
233 select DM_MMC if MMC
234 select DRAM_SUN8I_A83T
235 select PHY_SUN4I_USB
236 select SUNXI_GEN_SUN6I
237 select MMC_SUNXI_HAS_NEW_MODE
238 select MMC_SUNXI_HAS_MODE_SWITCH
239 select SUPPORT_SPL
243 select CPU_V7A
244 select CPU_V7_HAS_NONSEC
245 select CPU_V7_HAS_VIRT
246 select ARCH_SUPPORT_PSCI
247 select MACH_SUNXI_H3_H5
248 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
249 select DM_MMC if MMC
253 select CPU_V7A
254 select CPU_V7_HAS_NONSEC
255 select CPU_V7_HAS_VIRT
256 select ARCH_SUPPORT_PSCI
257 select SUNXI_GEN_SUN6I
258 select SUPPORT_SPL
259 select SUNXI_DRAM_DW
260 select SUNXI_DRAM_DW_32BIT
264 select CPU_V7A
265 select CPU_V7_HAS_NONSEC
266 select CPU_V7_HAS_VIRT
267 select ARCH_SUPPORT_PSCI
268 select DM_MMC if MMC
269 select SUNXI_GEN_SUN6I
270 select SUNXI_DRAM_DW
271 select SUNXI_DRAM_DW_16BIT
272 select SUPPORT_SPL
273 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
277 select CPU_V7A
278 select DRAM_SUN9I
279 select SUN6I_PRCM
280 select SUNXI_GEN_SUN6I
281 select SUN8I_RSB
282 select SUPPORT_SPL
283 select DM_MMC if MMC
287 select ARM64
288 select DM_I2C
289 select DM_MMC if MMC
290 select PHY_SUN4I_USB
291 select SUN6I_PRCM
292 select SUNXI_DE2
293 select SUNXI_GEN_SUN6I
294 select MMC_SUNXI_HAS_NEW_MODE
295 select SUPPORT_SPL
296 select SUNXI_DRAM_DW
297 select SUNXI_DRAM_DW_32BIT
298 select FIT
299 select SPL_LOAD_FIT
300 select SUNXI_A64_TIMER_ERRATUM
304 select ARM64
305 select MACH_SUNXI_H3_H5
306 select DM_MMC if MMC
307 select FIT
308 select SPL_LOAD_FIT
312 select ARM64
313 select SUPPORT_SPL
314 select DM_MMC if MMC
315 select FIT
316 select SPL_LOAD_FIT
317 select DRAM_SUN50I_H6
324 select SUN8I_RSB
325 select SUN6I_PRCM
335 select ENABLE_ARM_SOC_BOOT0_HOOK
336 ---help---
337 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
339 blob relies on this information to load and execute U-Boot.
340 Only needed on 64-bit Allwinner boards so far when using boot0.
346 select ENABLE_ARM_SOC_BOOT0_HOOK
347 ---help---
348 Insert some ARM32 code at the very beginning of the U-Boot binary
353 This allows both the SPL and the U-Boot proper to be entered in
373 select SUNXI_DRAM_DDR3
375 ---help---
381 select SUNXI_DRAM_LPDDR3
382 ---help---
388 select SUNXI_DRAM_DDR2
390 ---help---
391 This option is only for the DDR2 memory chip which is co-packaged in
401 ---help---
405 int "sunxi dram clock speed"
413 ---help---
414 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
416 (for DDR3-1600) are 312 to 792.
420 int "sunxi mbus clock speed"
422 ---help---
423 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
435 ---help---
444 ---help---
445 Select this to enable dram odt (on die termination).
452 ---help---
458 ---help---
464 clock speeds.
469 ---help---
473 means that the delay is 5 quarter-cycles for one lane (1.25
474 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
485 ---help---
486 Select the timings of the DDR3 chips.
490 ---help---
494 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
495 ---help---
496 Use the timings of the standard JEDEC DDR3-1066F speed bin for
497 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
499 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
500 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
501 that down binning to DDR3-1066F is supported (because DDR3-1066F
502 uses a bit faster timings than DDR3-1333H).
505 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
506 ---help---
509 DDR3-800E, DDR3-1066G or DDR3-1333J.
519 ---help---
520 Set the dram odt correction value (range -255 - 255). In allwinner
521 fex files, this option is found in bits 8-15 of the u32 odt_en variable
555 ---help---
557 console. Primarily useful only for low level u-boot debugging on
559 device disassembly and/or soldering. As the SD card can't be used
560 at the same time, the system can be only booted in the FEL mode.
566 ---help---
568 sub-optimal settings for newer kernels, only enable if needed.
581 ---help---
589 ---help---
595 ---help---
601 ---help---
607 ---help---
614 ---help---
620 ---help---
625 default -1
626 ---help---
628 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
634 ---help---
643 ---help---
650 ---help---
657 ---help---
665 ---help---
674 ---help---
680 ---help---
687 select CMD_I2C
688 ---help---
690 its clock and setting up the bus. This is especially useful on devices
697 select CMD_I2C
698 ---help---
704 select CMD_I2C
705 ---help---
712 select CMD_I2C
713 ---help---
722 select CMD_I2C
723 ---help---
731 select CMD_I2C
732 ---help---
737 bool "Enable support for gpio-s on axp PMICs"
739 ---help---
751 select VIDEO
754 ---help---
757 info on how to select the video output and mode.
763 ---help---
770 ---help---
777 ---help---
786 ---help---
796 ---help---
804 ---help---
811 ---help---
815 Also see: http://linux-sunxi.org/LCD
818 int "LCD panel display clock phase"
821 ---help---
822 Select LCD panel display clock phase shift, range 0-3.
828 ---help---
836 ---help---
844 ---help---
853 ---help---
861 ---help---
868 select CMD_I2C
869 ---help---
877 ---help---
885 ---help---
905 select DM_VIDEO
906 select DISPLAY
909 ---help---
917 ---help---
918 Select which type of LCD panel to support.
922 select VIDEO_LCD_IF_PARALLEL
926 select VIDEO_LCD_IF_LVDS
929 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
930 select VIDEO_LCD_SSD2828
931 select VIDEO_LCD_IF_PARALLEL
932 ---help---
936 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
937 select VIDEO_LCD_ANX9804
938 select VIDEO_LCD_IF_PARALLEL
939 select VIDEO_LCD_PANEL_I2C
940 ---help---
941 Select this for eDP LCD panels with 4 lanes running at 1.62G,
946 select VIDEO_LCD_HITACHI_TX18D42VM
947 select VIDEO_LCD_IF_LVDS
948 ---help---
953 select VIDEO_LCD_PANEL_I2C
954 select VIDEO_LCD_IF_PARALLEL
955 ---help---
970 int "GMAC Transmit Clock Delay Chain"
972 ---help---
973 Set the GMAC Transmit Clock Delay Chain value.
998 boards and can be differed by the DRAM size. Pine A64 has