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/openbmc/linux/sound/soc/codecs/
H A Dwm8990.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8990.c -- WM8990 ALSA Soc Audio driver
37 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
39 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
41 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
43 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
45 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
47 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
54 (struct soc_mixer_control *)kcontrol->private_value; in wm899x_outpga_put_volsw_vu()
55 int reg = mc->reg; in wm899x_outpga_put_volsw_vu()
[all …]
H A Dwm8991.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8991.c -- WM8991 ALSA Soc Audio driver
5 * Copyright 2007-2010 Wolfson Microelectronics PLC.
23 #include <sound/soc-dapm.h>
36 { 1, 0x0000 }, /* R1 - Power Management (1) */
37 { 2, 0x6000 }, /* R2 - Power Management (2) */
38 { 3, 0x0000 }, /* R3 - Power Management (3) */
39 { 4, 0x4050 }, /* R4 - Audio Interface (1) */
40 { 5, 0x4000 }, /* R5 - Audio Interface (2) */
41 { 6, 0x01C8 }, /* R6 - Clocking (1) */
[all …]
H A Dwm8400.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8400.c -- WM8400 ALSA Soc Audio driver
5 * Copyright 2008-11 Wolfson Microelectronics PLC.
18 #include <linux/mfd/wm8400-audio.h>
19 #include <linux/mfd/wm8400-private.h>
67 wm8400_reset_codec_reg_cache(wm8400->wm8400); in wm8400_component_reset()
70 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
72 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0);
74 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
76 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
[all …]
H A Disabelle.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * isabelle.c - Low power high fidelity audio codec driver
22 #include <sound/soc-dapm.h>
342 static const DECLARE_TLV_DB_SCALE(afm_amp_tlv, -3300, 300, 0);
343 static const DECLARE_TLV_DB_SCALE(dac_tlv, -1200, 200, 0);
344 static const DECLARE_TLV_DB_SCALE(hf_tlv, -5000, 200, 0);
346 /* from -63 to 0 dB in 1 dB steps */
347 static const DECLARE_TLV_DB_SCALE(dpga_tlv, -6300, 100, 1);
349 /* from -63 to 9 dB in 1 dB steps */
350 static const DECLARE_TLV_DB_SCALE(rx_tlv, -6300, 100, 1);
[all …]
H A Dadau1761.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2011-2013 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
125 static const DECLARE_TLV_DB_SCALE(adau1761_sing_in_tlv, -1500, 300, 1);
126 static const DECLARE_TLV_DB_SCALE(adau1761_diff_in_tlv, -1200, 75, 0);
127 static const DECLARE_TLV_DB_SCALE(adau1761_out_tlv, -5700, 100, 0);
128 static const DECLARE_TLV_DB_SCALE(adau1761_sidetone_tlv, -1800, 300, 1);
129 static const DECLARE_TLV_DB_SCALE(adau1761_boost_tlv, -600, 600, 1);
130 static const DECLARE_TLV_DB_SCALE(adau1761_pga_boost_tlv, -2000, 2000, 1);
132 static const DECLARE_TLV_DB_SCALE(adau1761_alc_max_gain_tlv, -1200, 600, 0);
[all …]
/openbmc/linux/drivers/regulator/
H A Danatop-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
30 bool bypass; member
43 if (anatop_reg->delay_bit_width && new_sel > old_sel) { in anatop_regmap_set_voltage_time_sel()
50 regmap_read(reg->regmap, anatop_reg->delay_reg, &val); in anatop_regmap_set_voltage_time_sel()
51 val = (val >> anatop_reg->delay_bit_shift) & in anatop_regmap_set_voltage_time_sel()
52 ((1 << anatop_reg->delay_bit_width) - 1); in anatop_regmap_set_voltage_time_sel()
53 ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES << in anatop_regmap_set_voltage_time_sel()
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
86 anatop_reg->sel = selector; in anatop_regmap_core_set_voltage_sel()
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/openbmc/qemu/docs/
H A Dbypass-iommu.txt1 BYPASS IOMMU PROPERTY
6 Traditionally, there is a global switch to enable/disable vIOMMU. All
8 is not flexible. We introduce this bypass iommu property to support
10 passthrough devices with no-iommu mode and devices go through vIOMMU in
14 determine whether the devices attached on the PCI host bridge will bypass
17 bypass vIOMMU. When bypass_iommu property is not set for a host bridge,
22 The bypass iommu feature support PXB host bridge and default main host
26 on AArch64. Other machine types do not support bypass iommu for default
29 1. The following is the bypass iommu options:
31 qemu -device pxb-pcie,bus_nr=0x10,addr=0x1,bypass_iommu=true
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/openbmc/linux/drivers/dma/fsl-dpaa2-qdma/
H A Ddpaa2-qdma.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 u32 rbpcmd; /* Route-by-port command */
36 #define QMAN_FD_FMT_ENABLE BIT(0) /* frame list table enable */
37 #define QMAN_FD_BMT_ENABLE BIT(15) /* bypass memory translation */
38 #define QMAN_FD_BMT_DISABLE (0) /* bypass memory translation */
43 #define QDMA_FINAL_BIT_ENABLE BIT(31) /* final bit enable */
51 #define QDMA_FD_SPF_ENALBE BIT(30) /* source prefetch enable */
62 #define QDMA_FL_BMT_ENABLE BIT(15) /* enable bypass memory translation */
63 #define QDMA_FL_BMT_DISABLE (0x0) /* enable bypass memory translation */
110 * dpaa2_qdma_priv - driver private data
/openbmc/linux/drivers/base/regmap/
H A Dregcache.c1 // SPDX-License-Identifier: GPL-2.0
32 if (!map->num_reg_defaults_raw) in regcache_hw_init()
33 return -EINVAL; in regcache_hw_init()
36 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) in regcache_hw_init()
37 if (regmap_readable(map, i * map->reg_stride) && in regcache_hw_init()
38 !regmap_volatile(map, i * map->reg_stride)) in regcache_hw_init()
41 /* all registers are unreadable or volatile, so just bypass */ in regcache_hw_init()
43 map->cache_bypass = true; in regcache_hw_init()
47 map->num_reg_defaults = count; in regcache_hw_init()
48 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default), in regcache_hw_init()
[all …]
/openbmc/linux/drivers/clk/ti/
H A Ddpll3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
52 dd = clk->dpll_data; in _omap3_dpll_write_clken()
54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()
55 v &= ~dd->enable_mask; in _omap3_dpll_write_clken()
56 v |= clken_bits << __ffs(dd->enable_mask); in _omap3_dpll_write_clken()
57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in _omap3_dpll_write_clken()
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H A Dclkt_dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
17 #include <linux/clk-provider.h>
30 #define DPLL_MULT_UNDERFLOW -1
51 #define DPLL_FINT_UNDERFLOW -1
52 #define DPLL_FINT_INVALID -2
57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
63 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
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/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dti-abb-regulator.txt4 - compatible: Should be one of:
5 - "ti,abb-v1" for older SoCs like OMAP3
6 - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
7 - "ti,abb-v3" for a generic definition where setup and control registers are
9 - reg: Address and length of the register set for the device. It contains
10 the information of registers in the same order as described by reg-names
11 - reg-names: Should contain the reg names
12 - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
13 - "control-address" - contains control register address of ABB module (ti,abb-v3)
14 - "setup-address" - contains setup register address of ABB module (ti,abb-v3)
[all …]
/openbmc/linux/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-hw.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2019-2020 NXP
11 #include "imx8-isi-core.h"
12 #include "imx8-isi-regs.h"
18 return readl(pipe->regs + reg); in mxc_isi_read()
23 writel(val, pipe->regs + reg); in mxc_isi_write()
26 /* -----------------------------------------------------------------------------
33 if (pipe->isi->pdata->has_36bit_dma) in mxc_isi_channel_set_inbuf()
53 if (pipe->isi->pdata->has_36bit_dma) { in mxc_isi_channel_set_outbuf()
69 if (pipe->isi->pdata->has_36bit_dma) { in mxc_isi_channel_set_outbuf()
[all …]
/openbmc/linux/include/linux/clk/
H A Dti.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/clk-provider.h>
14 * struct clk_omap_reg - OMAP register declaration
26 * struct dpll_data - DPLL registers and integration data
30 * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input
40 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
42 * @min_divider: minimum valid non-bypass divider value (actual)
43 * @max_divider: maximum valid non-bypass divider value (actual)
53 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
55 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_link_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
37 enc10->base.ctx
39 enc10->base.ctx->logger
42 (enc10->link_regs->reg)
46 enc10->link_shift->field_name, enc10->link_mask->field_name
52 * ASIC-dependent, actual values for register programming
98 struct dc_bios *bp = enc10->base.ctx->dc_bios; in link_transmitter_control()
100 result = bp->funcs->transmitter_control(bp, cntl); in link_transmitter_control()
107 bool enable) in enable_phy_bypass_mode() argument
112 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); in enable_phy_bypass_mode()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_dcb_82599.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
9 * 1 WSP - Weighted Strict Priority
12 * 1 WRR - Weighted Round Robin
16 #define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */
17 #define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must
30 #define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */
31 #define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */
34 * buffers enable
37 * (RSS) enable
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/openbmc/linux/arch/arm/mach-davinci/
H A Dsleep.S1 /* SPDX-License-Identifier: GPL-2.0-only */
41 stmfd sp!, {r0-r12, lr} @ save registers on stack
46 ldmia r0, {r0-r4}
49 * Switch DDR to self-refresh mode.
77 /* Put the DDR PLL in bypass and power down */
83 /* Wait for PLL to switch to bypass */
101 /* Clear sleep enable */
132 /* Remove PLL from bypass mode */
144 /* Enable VCLK */
146 /* Enable DDR2 LPSC */
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
57 enc110->base.ctx
59 enc110->base.ctx->logger
62 (enc110->link_regs->reg)
65 (enc110->aux_regs->reg)
68 (enc110->hpd_regs->reg)
75 * ASIC-dependent, actual values for register programming
91 (reg + enc110->offsets.dig)
94 (reg + enc110->offsets.dp)
127 struct dc_bios *bp = enc110->base.ctx->dc_bios; in link_transmitter_control()
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/openbmc/linux/drivers/iommu/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
34 Enable support for the ARM long descriptor pagetable format.
36 sizes at both stage-1 and stage-2, as well as address spaces
37 up to 48-bits in size.
43 Enable self-tests for LPAE page table allocator. This performs
44 a series of page-table consistency checks during boot.
53 Enable support for the ARM Short-descriptor pagetable format.
54 This supports 32-bit virtual and physical addresses mapped using
55 2-level tables with 4KB pages/1MB sections, and contiguous entries
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/thunder/
H A Dthunder_xcv.c1 // SPDX-License-Identifier: GPL-2.0-only
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
81 /* Configure DLL - enable or bypass in xcv_init_hw()
82 * TX no bypass, RX bypass in xcv_init_hw()
84 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
87 writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
89 /* Enable compensation controller and force the in xcv_init_hw()
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
46 * H/W requires a 5us delay between disabling the bypass and in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
[all …]
/openbmc/openbmc/poky/meta/recipes-core/glibc/
H A Dglibc_2.40.bb2 require glibc-version.inc
4 # glibc https://web.nvd.nist.gov/view/vuln/detail?vulnId=CVE-2019-1010022
5 # glibc https://web.nvd.nist.gov/view/vuln/detail?vulnId=CVE-2019-1010023
6 # glibc https://web.nvd.nist.gov/view/vuln/detail?vulnId=CVE-2019-1010024
8 CVE_STATUS_RECIPE = "CVE-2019-1010022 CVE-2019-1010023 CVE-2019-1010024"
11 this is being treated as a non-security bug and no real threat."
13 # glibc https://web.nvd.nist.gov/view/vuln/detail?vulnId=CVE-2019-1010025
15 CVE_STATUS[CVE-2019-1010025] = "disputed: \
16 Allows for ASLR bypass so can bypass some hardening, not an exploit in itself, may allow \
17 easier access for another. 'ASLR bypass itself is not a vulnerability.'"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/power/supply/
H A Dbq25980.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
15 for use in high-power density portable electronics. These inductorless
20 - $ref: power-supply.yaml#
25 - ti,bq25980
26 - ti,bq25975
27 - ti,bq25960
32 ti,watchdog-timeout-ms:
[all …]
/openbmc/linux/Documentation/admin-guide/device-mapper/
H A Ddm-dust.rst1 dm-dust
5 locations, and the ability to enable the emulation of the failures
27 With dm-dust, the user can use the "addbadblock" and "removebadblock"
29 "enable" and "disable" messages to modulate the state of whether the
31 This allows the pre-writing of test data and metadata prior to
35 ----------------
51 ------------------
53 First, find the size (in 512-byte sectors) of the device to be used::
55 $ sudo blockdev --getsz /dev/vdb1
58 Create the dm-dust device:
[all …]
/openbmc/linux/drivers/pwm/
H A Dpwm-sun4i.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
47 #define PWM_PRD(prd) (((prd) - 1) << 16)
101 return readl(chip->base + offset); in sun4i_pwm_readl()
107 writel(val, chip->base + offset); in sun4i_pwm_writel()
119 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_get_state()
121 return -EINVAL; in sun4i_pwm_get_state()
126 * PWM chapter in H6 manual has a diagram which explains that if bypass in sun4i_pwm_get_state()
128 * proved that also enable bit is ignored in this case. in sun4i_pwm_get_state()
[all …]

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