xref: /openbmc/linux/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt (revision 5b45fe6b39e1d01c45de7b8e6d3ff72585eee6cf)
140b1936eSAndrii.TseglytskyiAdaptive Body Bias(ABB) SoC internal LDO regulator for Texas Instruments SoCs
240b1936eSAndrii.Tseglytskyi
340b1936eSAndrii.TseglytskyiRequired Properties:
440b1936eSAndrii.Tseglytskyi- compatible: Should be one of:
540b1936eSAndrii.Tseglytskyi  - "ti,abb-v1" for older SoCs like OMAP3
640b1936eSAndrii.Tseglytskyi  - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
76127daa8SNishanth Menon  - "ti,abb-v3" for a generic definition where setup and control registers are
86127daa8SNishanth Menon     provided (example: DRA7)
940b1936eSAndrii.Tseglytskyi- reg: Address and length of the register set for the device. It contains
1040b1936eSAndrii.Tseglytskyi  the information of registers in the same order as described by reg-names
1140b1936eSAndrii.Tseglytskyi- reg-names: Should contain the reg names
126127daa8SNishanth Menon  - "base-address"	- contains base address of ABB module (ti,abb-v1,ti,abb-v2)
136127daa8SNishanth Menon  - "control-address"	- contains control register address of ABB module (ti,abb-v3)
146127daa8SNishanth Menon  - "setup-address"	- contains setup register address of ABB module (ti,abb-v3)
1540b1936eSAndrii.Tseglytskyi  - "int-address"	- contains address of interrupt register for ABB module
1640b1936eSAndrii.Tseglytskyi  (also see Optional properties)
171a4d5a3eSGeert Uytterhoeven- #address-cells: should be 0
181a4d5a3eSGeert Uytterhoeven- #size-cells: should be 0
1940b1936eSAndrii.Tseglytskyi- clocks: should point to the clock node used by ABB module
2040b1936eSAndrii.Tseglytskyi- ti,settling-time: Settling time in uSecs from SoC documentation for ABB module
2140b1936eSAndrii.Tseglytskyi	to settle down(target time for SR2_WTCNT_VALUE).
2240b1936eSAndrii.Tseglytskyi- ti,clock-cycles: SoC specific data about count of system ti,clock-cycles used for
2340b1936eSAndrii.Tseglytskyi	computing settling time from SoC Documentation for ABB module(clock
2440b1936eSAndrii.Tseglytskyi	cycles for SR2_WTCNT_VALUE).
2540b1936eSAndrii.Tseglytskyi- ti,tranxdone-status-mask: Mask to the int-register to write-to-clear mask
2640b1936eSAndrii.Tseglytskyi	indicating LDO tranxdone (operation complete).
2740b1936eSAndrii.Tseglytskyi- ti,abb_info: An array of 6-tuples u32 items providing information about ABB
2840b1936eSAndrii.Tseglytskyi	configuration needed per operational voltage of the device.
2940b1936eSAndrii.Tseglytskyi	Each item consists of the following in the same order:
3040b1936eSAndrii.Tseglytskyi	volt: voltage in uV - Only used to index ABB information.
3140b1936eSAndrii.Tseglytskyi	ABB mode: one of the following:
3240b1936eSAndrii.Tseglytskyi		0-bypass
3340b1936eSAndrii.Tseglytskyi		1-Forward Body Bias(FBB)
3440b1936eSAndrii.Tseglytskyi		3-Reverse Body Bias(RBB)
3540b1936eSAndrii.Tseglytskyi	efuse:	(see Optional properties)
3640b1936eSAndrii.Tseglytskyi	RBB enable efuse Mask:	(See Optional properties)
3740b1936eSAndrii.Tseglytskyi	FBB enable efuse Mask:	(See Optional properties)
3840b1936eSAndrii.Tseglytskyi	Vset value efuse Mask:	(See Optional properties)
3940b1936eSAndrii.Tseglytskyi
4040b1936eSAndrii.Tseglytskyi	NOTE: If more than 1 entry is present, then regulator is setup to change
4140b1936eSAndrii.Tseglytskyi	      voltage, allowing for various modes to be selected indexed off
4240b1936eSAndrii.Tseglytskyi	      the regulator. Further, ABB LDOs are considered always-on by
4340b1936eSAndrii.Tseglytskyi	      default.
4440b1936eSAndrii.Tseglytskyi
4540b1936eSAndrii.TseglytskyiOptional Properties:
4640b1936eSAndrii.Tseglytskyi- reg-names: In addition to the required properties, the following are optional
4740b1936eSAndrii.Tseglytskyi  - "efuse-address"	- Contains efuse base address used to pick up ABB info.
48*505d3085SMasahiro Yamada  - "ldo-address"	- Contains address of ABB LDO override register.
4940b1936eSAndrii.Tseglytskyi	"efuse-address" is required for this.
5040b1936eSAndrii.Tseglytskyi- ti,ldovbb-vset-mask	- Required if ldo-address is set, mask for LDO override
5140b1936eSAndrii.Tseglytskyi	register to provide override vset value.
5240b1936eSAndrii.Tseglytskyi- ti,ldovbb-override-mask - Required if ldo-address is set, mask for LDO
5340b1936eSAndrii.Tseglytskyi	override register to enable override vset value.
5440b1936eSAndrii.Tseglytskyi- ti,abb_opp_sel: Addendum to the description in required properties
5540b1936eSAndrii.Tseglytskyi	efuse: Mandatory if 'efuse-address' register is defined. Provides offset
5640b1936eSAndrii.Tseglytskyi	       from efuse-address to pick up ABB characteristics. Set to 0 if
5740b1936eSAndrii.Tseglytskyi	       'efuse-address' is not defined.
5840b1936eSAndrii.Tseglytskyi	RBB enable efuse Mask:	Optional if 'efuse-address' register is defined.
5940b1936eSAndrii.Tseglytskyi		'ABB mode' is force set to RBB mode if value at "efuse-address"
6040b1936eSAndrii.Tseglytskyi		+ efuse maps to RBB mask. Set to 0 to ignore this.
6140b1936eSAndrii.Tseglytskyi	FBB enable efuse Mask:	Optional if 'efuse-address' register is defined.
6240b1936eSAndrii.Tseglytskyi		'ABB mode' is force set to FBB mode if value at "efuse-address"
6340b1936eSAndrii.Tseglytskyi		+ efuse maps to FBB mask (valid only if RBB mask does not match)
6440b1936eSAndrii.Tseglytskyi		Set to 0 to ignore this.
6540b1936eSAndrii.Tseglytskyi	Vset value efuse Mask:	Mandatory if ldo-address is set. Picks up from
6640b1936eSAndrii.Tseglytskyi		efuse the value to set in 'ti,ldovbb-vset-mask' at ldo-address.
6740b1936eSAndrii.Tseglytskyi
6840b1936eSAndrii.TseglytskyiExample #1: Simplest configuration (no efuse data, hard coded ABB table):
6940b1936eSAndrii.Tseglytskyiabb_x: regulator-abb-x {
7040b1936eSAndrii.Tseglytskyi	compatible = "ti,abb-v1";
7140b1936eSAndrii.Tseglytskyi	regulator-name = "abb_x";
721a4d5a3eSGeert Uytterhoeven	#address-cells = <0>;
7340b1936eSAndrii.Tseglytskyi	#size-cells = <0>;
7440b1936eSAndrii.Tseglytskyi	reg = <0x483072f0 0x8>, <0x48306818 0x4>;
7540b1936eSAndrii.Tseglytskyi	reg-names = "base-address", "int-address";
7640b1936eSAndrii.Tseglytskyi	ti,tranxdone-status-mask = <0x4000000>;
7740b1936eSAndrii.Tseglytskyi	clocks = <&sysclk>;
7840b1936eSAndrii.Tseglytskyi	ti,settling-time = <30>;
7940b1936eSAndrii.Tseglytskyi	ti,clock-cycles = <8>;
8040b1936eSAndrii.Tseglytskyi	ti,abb_info = <
8140b1936eSAndrii.Tseglytskyi	/* uV		ABB	efuse	rbb_m	fbb_m	vset_m */
8240b1936eSAndrii.Tseglytskyi	1012500		0	0	0	0	0 /* Bypass */
8340b1936eSAndrii.Tseglytskyi	1200000		3	0	0	0	0 /* RBB mandatory */
8440b1936eSAndrii.Tseglytskyi	1320000		1	0	0	0	0 /* FBB mandatory */
8540b1936eSAndrii.Tseglytskyi	>;
8640b1936eSAndrii.Tseglytskyi};
8740b1936eSAndrii.Tseglytskyi
8840b1936eSAndrii.TseglytskyiExample #2: Efuse bits contain ABB mode setting (no LDO override capability)
8940b1936eSAndrii.Tseglytskyiabb_y: regulator-abb-y {
9040b1936eSAndrii.Tseglytskyi	compatible = "ti,abb-v2";
9140b1936eSAndrii.Tseglytskyi	regulator-name = "abb_y";
921a4d5a3eSGeert Uytterhoeven	#address-cells = <0>;
9340b1936eSAndrii.Tseglytskyi	#size-cells = <0>;
9440b1936eSAndrii.Tseglytskyi	reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>, <0x4A002268 0x8>;
9540b1936eSAndrii.Tseglytskyi	reg-names = "base-address", "int-address", "efuse-address";
9640b1936eSAndrii.Tseglytskyi	ti,tranxdone-status-mask = <0x4000000>;
9740b1936eSAndrii.Tseglytskyi	clocks = <&sysclk>;
9840b1936eSAndrii.Tseglytskyi	ti,settling-time = <50>;
9940b1936eSAndrii.Tseglytskyi	ti,clock-cycles = <16>;
10040b1936eSAndrii.Tseglytskyi	ti,abb_info = <
10140b1936eSAndrii.Tseglytskyi	/* uV		ABB	efuse	rbb_m	fbb_m	vset_m */
10240b1936eSAndrii.Tseglytskyi	975000		0	0	0	0	0 /* Bypass */
10340b1936eSAndrii.Tseglytskyi	1012500		0	0	0x40000	0	0 /* RBB optional */
10440b1936eSAndrii.Tseglytskyi	1200000		0	0x4	0	0x40000	0 /* FBB optional */
10540b1936eSAndrii.Tseglytskyi	1320000		1	0	0	0	0 /* FBB mandatory */
10640b1936eSAndrii.Tseglytskyi	>;
10740b1936eSAndrii.Tseglytskyi};
10840b1936eSAndrii.Tseglytskyi
10940b1936eSAndrii.TseglytskyiExample #3: Efuse bits contain ABB mode setting and LDO override capability
11040b1936eSAndrii.Tseglytskyiabb_z: regulator-abb-z {
11140b1936eSAndrii.Tseglytskyi	compatible = "ti,abb-v2";
11240b1936eSAndrii.Tseglytskyi	regulator-name = "abb_z";
1131a4d5a3eSGeert Uytterhoeven	#address-cells = <0>;
11440b1936eSAndrii.Tseglytskyi	#size-cells = <0>;
11540b1936eSAndrii.Tseglytskyi	reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
11640b1936eSAndrii.Tseglytskyi	      <0x4a002194 0x8>, <0x4ae0C314 0x4>;
11740b1936eSAndrii.Tseglytskyi	reg-names = "base-address", "int-address",
11840b1936eSAndrii.Tseglytskyi		    "efuse-address", "ldo-address";
11940b1936eSAndrii.Tseglytskyi	ti,tranxdone-status-mask = <0x8000000>;
12040b1936eSAndrii.Tseglytskyi	/* LDOVBBMM_MUX_CTRL */
12140b1936eSAndrii.Tseglytskyi	ti,ldovbb-override-mask = <0x400>;
12240b1936eSAndrii.Tseglytskyi	/* LDOVBBMM_VSET_OUT */
12340b1936eSAndrii.Tseglytskyi	ti,ldovbb-vset-mask = <0x1F>;
12440b1936eSAndrii.Tseglytskyi	clocks = <&sysclk>;
12540b1936eSAndrii.Tseglytskyi	ti,settling-time = <50>;
12640b1936eSAndrii.Tseglytskyi	ti,clock-cycles = <16>;
12740b1936eSAndrii.Tseglytskyi	ti,abb_info = <
12840b1936eSAndrii.Tseglytskyi	/* uV	ABB	efuse	rbb_m	fbb_m	vset_m */
12940b1936eSAndrii.Tseglytskyi	975000	0	0	0	0	0	/* Bypass */
13040b1936eSAndrii.Tseglytskyi	1200000	0	0x4	0	0x40000	0x1f00	/* FBB optional, vset */
13140b1936eSAndrii.Tseglytskyi	>;
13240b1936eSAndrii.Tseglytskyi};
133