Lines Matching +full:bypass +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0
32 if (!map->num_reg_defaults_raw) in regcache_hw_init()
33 return -EINVAL; in regcache_hw_init()
36 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) in regcache_hw_init()
37 if (regmap_readable(map, i * map->reg_stride) && in regcache_hw_init()
38 !regmap_volatile(map, i * map->reg_stride)) in regcache_hw_init()
41 /* all registers are unreadable or volatile, so just bypass */ in regcache_hw_init()
43 map->cache_bypass = true; in regcache_hw_init()
47 map->num_reg_defaults = count; in regcache_hw_init()
48 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default), in regcache_hw_init()
50 if (!map->reg_defaults) in regcache_hw_init()
51 return -ENOMEM; in regcache_hw_init()
53 if (!map->reg_defaults_raw) { in regcache_hw_init()
54 bool cache_bypass = map->cache_bypass; in regcache_hw_init()
55 dev_warn(map->dev, "No cache defaults, reading back from HW\n"); in regcache_hw_init()
57 /* Bypass the cache access till data read from HW */ in regcache_hw_init()
58 map->cache_bypass = true; in regcache_hw_init()
59 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL); in regcache_hw_init()
61 ret = -ENOMEM; in regcache_hw_init()
65 map->cache_size_raw); in regcache_hw_init()
66 map->cache_bypass = cache_bypass; in regcache_hw_init()
68 map->reg_defaults_raw = tmp_buf; in regcache_hw_init()
69 map->cache_free = true; in regcache_hw_init()
76 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) { in regcache_hw_init()
77 reg = i * map->reg_stride; in regcache_hw_init()
85 if (map->reg_defaults_raw) { in regcache_hw_init()
86 val = regcache_get_val(map, map->reg_defaults_raw, i); in regcache_hw_init()
88 bool cache_bypass = map->cache_bypass; in regcache_hw_init()
90 map->cache_bypass = true; in regcache_hw_init()
92 map->cache_bypass = cache_bypass; in regcache_hw_init()
94 dev_err(map->dev, "Failed to read %d: %d\n", in regcache_hw_init()
100 map->reg_defaults[j].reg = reg; in regcache_hw_init()
101 map->reg_defaults[j].def = val; in regcache_hw_init()
108 kfree(map->reg_defaults); in regcache_hw_init()
119 if (map->cache_type == REGCACHE_NONE) { in regcache_init()
120 if (config->reg_defaults || config->num_reg_defaults_raw) in regcache_init()
121 dev_warn(map->dev, in regcache_init()
124 map->cache_bypass = true; in regcache_init()
128 if (config->reg_defaults && !config->num_reg_defaults) { in regcache_init()
129 dev_err(map->dev, in regcache_init()
131 return -EINVAL; in regcache_init()
134 if (config->num_reg_defaults && !config->reg_defaults) { in regcache_init()
135 dev_err(map->dev, in regcache_init()
137 return -EINVAL; in regcache_init()
140 for (i = 0; i < config->num_reg_defaults; i++) in regcache_init()
141 if (config->reg_defaults[i].reg % map->reg_stride) in regcache_init()
142 return -EINVAL; in regcache_init()
145 if (cache_types[i]->type == map->cache_type) in regcache_init()
149 dev_err(map->dev, "Could not match cache type: %d\n", in regcache_init()
150 map->cache_type); in regcache_init()
151 return -EINVAL; in regcache_init()
154 map->num_reg_defaults = config->num_reg_defaults; in regcache_init()
155 map->num_reg_defaults_raw = config->num_reg_defaults_raw; in regcache_init()
156 map->reg_defaults_raw = config->reg_defaults_raw; in regcache_init()
157 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8); in regcache_init()
158 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw; in regcache_init()
160 map->cache = NULL; in regcache_init()
161 map->cache_ops = cache_types[i]; in regcache_init()
163 if (!map->cache_ops->read || in regcache_init()
164 !map->cache_ops->write || in regcache_init()
165 !map->cache_ops->name) in regcache_init()
166 return -EINVAL; in regcache_init()
172 if (config->reg_defaults) { in regcache_init()
173 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults * in regcache_init()
176 return -ENOMEM; in regcache_init()
177 map->reg_defaults = tmp_buf; in regcache_init()
178 } else if (map->num_reg_defaults_raw) { in regcache_init()
186 if (map->cache_bypass) in regcache_init()
190 if (!map->max_register && map->num_reg_defaults_raw) in regcache_init()
191 map->max_register = (map->num_reg_defaults_raw - 1) * map->reg_stride; in regcache_init()
193 if (map->cache_ops->init) { in regcache_init()
194 dev_dbg(map->dev, "Initializing %s cache\n", in regcache_init()
195 map->cache_ops->name); in regcache_init()
196 ret = map->cache_ops->init(map); in regcache_init()
203 kfree(map->reg_defaults); in regcache_init()
204 if (map->cache_free) in regcache_init()
205 kfree(map->reg_defaults_raw); in regcache_init()
212 if (map->cache_type == REGCACHE_NONE) in regcache_exit()
215 BUG_ON(!map->cache_ops); in regcache_exit()
217 kfree(map->reg_defaults); in regcache_exit()
218 if (map->cache_free) in regcache_exit()
219 kfree(map->reg_defaults_raw); in regcache_exit()
221 if (map->cache_ops->exit) { in regcache_exit()
222 dev_dbg(map->dev, "Destroying %s cache\n", in regcache_exit()
223 map->cache_ops->name); in regcache_exit()
224 map->cache_ops->exit(map); in regcache_exit()
229 * regcache_read - Fetch the value of a given register from the cache.
242 if (map->cache_type == REGCACHE_NONE) in regcache_read()
243 return -EINVAL; in regcache_read()
245 BUG_ON(!map->cache_ops); in regcache_read()
248 ret = map->cache_ops->read(map, reg, value); in regcache_read()
256 return -EINVAL; in regcache_read()
260 * regcache_write - Set the value of a given register in the cache.
271 if (map->cache_type == REGCACHE_NONE) in regcache_write()
274 BUG_ON(!map->cache_ops); in regcache_write()
277 return map->cache_ops->write(map, reg, value); in regcache_write()
291 if (!map->no_sync_defaults) in regcache_reg_needs_sync()
296 if (ret >= 0 && val == map->reg_defaults[ret].def) in regcache_reg_needs_sync()
306 for (reg = min; reg <= max; reg += map->reg_stride) { in regcache_default_sync()
315 if (ret == -ENOENT) in regcache_default_sync()
323 map->cache_bypass = true; in regcache_default_sync()
325 map->cache_bypass = false; in regcache_default_sync()
327 dev_err(map->dev, "Unable to sync register %#x. %d\n", in regcache_default_sync()
331 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val); in regcache_default_sync()
343 * regcache_sync - Sync the register cache with the hardware.
358 bool bypass; in regcache_sync() local
361 if (WARN_ON(map->cache_type == REGCACHE_NONE)) in regcache_sync()
362 return -EINVAL; in regcache_sync()
364 BUG_ON(!map->cache_ops); in regcache_sync()
366 map->lock(map->lock_arg); in regcache_sync()
367 /* Remember the initial bypass state */ in regcache_sync()
368 bypass = map->cache_bypass; in regcache_sync()
369 dev_dbg(map->dev, "Syncing %s cache\n", in regcache_sync()
370 map->cache_ops->name); in regcache_sync()
371 name = map->cache_ops->name; in regcache_sync()
374 if (!map->cache_dirty) in regcache_sync()
378 map->cache_bypass = true; in regcache_sync()
379 for (i = 0; i < map->patch_regs; i++) { in regcache_sync()
380 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def); in regcache_sync()
382 dev_err(map->dev, "Failed to write %x = %x: %d\n", in regcache_sync()
383 map->patch[i].reg, map->patch[i].def, ret); in regcache_sync()
387 map->cache_bypass = false; in regcache_sync()
389 if (map->cache_ops->sync) in regcache_sync()
390 ret = map->cache_ops->sync(map, 0, map->max_register); in regcache_sync()
392 ret = regcache_default_sync(map, 0, map->max_register); in regcache_sync()
395 map->cache_dirty = false; in regcache_sync()
398 /* Restore the bypass state */ in regcache_sync()
399 map->cache_bypass = bypass; in regcache_sync()
400 map->no_sync_defaults = false; in regcache_sync()
408 rb_for_each(node, 0, &map->range_tree, rbtree_all) { in regcache_sync()
413 if (regcache_read(map, this->selector_reg, &i) != 0) in regcache_sync()
416 ret = _regmap_write(map, this->selector_reg, i); in regcache_sync()
418 dev_err(map->dev, "Failed to write %x = %x: %d\n", in regcache_sync()
419 this->selector_reg, i, ret); in regcache_sync()
424 map->unlock(map->lock_arg); in regcache_sync()
435 * regcache_sync_region - Sync part of the register cache with the hardware.
441 * Write all non-default register values in the specified region to
451 bool bypass; in regcache_sync_region() local
453 if (WARN_ON(map->cache_type == REGCACHE_NONE)) in regcache_sync_region()
454 return -EINVAL; in regcache_sync_region()
456 BUG_ON(!map->cache_ops); in regcache_sync_region()
458 map->lock(map->lock_arg); in regcache_sync_region()
460 /* Remember the initial bypass state */ in regcache_sync_region()
461 bypass = map->cache_bypass; in regcache_sync_region()
463 name = map->cache_ops->name; in regcache_sync_region()
464 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max); in regcache_sync_region()
468 if (!map->cache_dirty) in regcache_sync_region()
471 map->async = true; in regcache_sync_region()
473 if (map->cache_ops->sync) in regcache_sync_region()
474 ret = map->cache_ops->sync(map, min, max); in regcache_sync_region()
479 /* Restore the bypass state */ in regcache_sync_region()
480 map->cache_bypass = bypass; in regcache_sync_region()
481 map->async = false; in regcache_sync_region()
482 map->no_sync_defaults = false; in regcache_sync_region()
483 map->unlock(map->lock_arg); in regcache_sync_region()
494 * regcache_drop_region - Discard part of the register cache
509 if (!map->cache_ops || !map->cache_ops->drop) in regcache_drop_region()
510 return -EINVAL; in regcache_drop_region()
512 map->lock(map->lock_arg); in regcache_drop_region()
516 ret = map->cache_ops->drop(map, min, max); in regcache_drop_region()
518 map->unlock(map->lock_arg); in regcache_drop_region()
525 * regcache_cache_only - Put a register map into cache only mode
528 * @enable: flag if changes should be written to the hardware
536 void regcache_cache_only(struct regmap *map, bool enable) in regcache_cache_only() argument
538 map->lock(map->lock_arg); in regcache_cache_only()
539 WARN_ON(map->cache_type != REGCACHE_NONE && in regcache_cache_only()
540 map->cache_bypass && enable); in regcache_cache_only()
541 map->cache_only = enable; in regcache_cache_only()
542 trace_regmap_cache_only(map, enable); in regcache_cache_only()
543 map->unlock(map->lock_arg); in regcache_cache_only()
548 * regcache_mark_dirty - Indicate that HW registers were reset to default values
553 * on resume, regcache_sync() knows to write out all non-default values
562 map->lock(map->lock_arg); in regcache_mark_dirty()
563 map->cache_dirty = true; in regcache_mark_dirty()
564 map->no_sync_defaults = true; in regcache_mark_dirty()
565 map->unlock(map->lock_arg); in regcache_mark_dirty()
570 * regcache_cache_bypass - Put a register map into cache bypass mode
573 * @enable: flag if changes should not be written to the cache
575 * When a register map is marked with the cache bypass option, writes
580 void regcache_cache_bypass(struct regmap *map, bool enable) in regcache_cache_bypass() argument
582 map->lock(map->lock_arg); in regcache_cache_bypass()
583 WARN_ON(map->cache_only && enable); in regcache_cache_bypass()
584 map->cache_bypass = enable; in regcache_cache_bypass()
585 trace_regmap_cache_bypass(map, enable); in regcache_cache_bypass()
586 map->unlock(map->lock_arg); in regcache_cache_bypass()
591 * regcache_reg_cached - Check if a register is cached
603 map->lock(map->lock_arg); in regcache_reg_cached()
607 map->unlock(map->lock_arg); in regcache_reg_cached()
617 if (map->format.format_val) { in regcache_set_val()
618 map->format.format_val(base + (map->cache_word_size * idx), in regcache_set_val()
623 switch (map->cache_word_size) { in regcache_set_val()
651 return -EINVAL; in regcache_get_val()
654 if (map->format.parse_val) in regcache_get_val()
655 return map->format.parse_val(regcache_get_val_addr(map, base, in regcache_get_val()
658 switch (map->cache_word_size) { in regcache_get_val()
678 return -1; in regcache_get_val()
686 return _a->reg - _b->reg; in regcache_default_cmp()
697 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults, in regcache_lookup_reg()
701 return r - map->reg_defaults; in regcache_lookup_reg()
703 return -ENOENT; in regcache_lookup_reg()
721 map->cache_bypass = true; in regcache_sync_val()
725 map->cache_bypass = false; in regcache_sync_val()
728 dev_err(map->dev, "Unable to sync register %#x. %d\n", in regcache_sync_val()
732 dev_dbg(map->dev, "Synced register %#x, value %#x\n", in regcache_sync_val()
747 regtmp = block_base + (i * map->reg_stride); in regcache_sync_block_single()
765 size_t val_bytes = map->format.val_bytes; in regcache_sync_block_raw_flush()
771 count = (cur - base) / map->reg_stride; in regcache_sync_block_raw_flush()
773 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n", in regcache_sync_block_raw_flush()
774 count * val_bytes, count, base, cur - map->reg_stride); in regcache_sync_block_raw_flush()
776 map->cache_bypass = true; in regcache_sync_block_raw_flush()
780 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n", in regcache_sync_block_raw_flush()
781 base, cur - map->reg_stride, ret); in regcache_sync_block_raw_flush()
783 map->cache_bypass = false; in regcache_sync_block_raw_flush()
802 regtmp = block_base + (i * map->reg_stride); in regcache_sync_block_raw()
829 map->reg_stride); in regcache_sync_block_raw()
837 if (regmap_can_raw_write(map) && !map->use_single_write) in regcache_sync_block()