| /openbmc/linux/drivers/dma/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
17 config DMADEVICES_DEBUG
24 config DMADEVICES_VDEBUG
38 config ASYNC_TX_ENABLE_CHANNEL_SWITCH
41 config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
44 config DMA_ENGINE
47 config DMA_VIRTUAL_CHANNELS
50 config DMA_ACPI
54 config DMA_OF
60 config ALTERA_MSGDMA
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| /openbmc/u-boot/drivers/axi/ |
| H A D | Kconfig | 1 menuconfig AXI config
2 bool "AXI bus drivers"
4 Support AXI (Advanced eXtensible Interface) busses, a on-chip
15 if AXI
17 config IHS_AXI
18 bool "Enable IHS AXI driver"
22 Interface (IHS AXI) bus on a gdsys IHS FPGA used to communicate with
25 config AXI_SANDBOX
26 bool "Enable AXI sandbox driver"
29 Support AXI (Advanced eXtensible Interface) emulation for the sandbox
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| /openbmc/linux/sound/soc/adi/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 config SND_SOC_ADI
7 config SND_SOC_ADI_AXI_I2S
8 tristate "AXI-I2S support"
13 ASoC driver for the Analog Devices AXI-I2S softcore peripheral.
15 config SND_SOC_ADI_AXI_SPDIF
16 tristate "AXI-SPDIF support"
21 ASoC driver for the Analog Devices AXI-SPDIF softcore peripheral.
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | qcom,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - enum:
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq6018
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| /openbmc/linux/drivers/bus/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
8 config ARM_CCI
11 config ARM_CCI400_COMMON
15 config ARM_CCI400_PORT_CTRL
23 config ARM_INTEGRATOR_LM
32 config BRCMSTB_GISB_ARB
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
41 config BT1_APB
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
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| /openbmc/linux/drivers/staging/axis-fifo/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # "Xilinx AXI-Stream FIFO IP core driver"
5 config XIL_AXIS_FIFO
6 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.
10 The AXI Streaming FIFO allows memory mapped access to a AXI Streaming
11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
12 to the AXI Ethernet without the need to use DMA.
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| /openbmc/linux/drivers/pci/controller/mobiveil/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "Mobiveil-based PCIe controllers"
6 config PCIE_MOBIVEIL
9 config PCIE_MOBIVEIL_HOST
14 config PCIE_LAYERSCAPE_GEN4
23 config PCIE_MOBIVEIL_PLAT
24 bool "Mobiveil AXI PCIe controller"
30 Say Y here if you want to enable support for the Mobiveil AXI PCIe
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| /openbmc/linux/drivers/net/ethernet/freescale/fman/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 config FSL_FMAN
11 Freescale Data-Path Acceleration Architecture Frame Manager
14 config DPAA_ERRATUM_A050385
26 such that more than 17 AXI transactions are in flight from FMAN
30 1. FMAN AXI transaction crosses 4K address boundary (Errata
32 2. FMAN DMA address for an AXI transaction is not 16 byte
33 aligned, i.e. the last 4 bits of an address are non-zero
40 stress with multiple ports injecting line-rate traffic.
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| /openbmc/linux/drivers/pci/controller/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
6 config PCI_AARDVARK
17 config PCIE_ALTERA
24 config PCIE_ALTERA_MSI
32 config PCIE_APPLE_MSI_DOORBELL_ADDR
37 config PCIE_APPLE
45 system-on-chips, like the Apple M1. This is required for the USB
46 type-A ports, Ethernet, Wi-Fi, and Bluetooth.
50 config PCI_VERSATILE
54 config PCIE_BRCMSTB
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| /openbmc/linux/drivers/net/ethernet/xilinx/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 config NET_VENDOR_XILINX
19 config XILINX_EMACLITE
26 config XILINX_AXI_EMAC
27 tristate "Xilinx 10/100/1000 AXI Ethernet support"
32 AXI bus interface used in Xilinx Virtex FPGAs and Soc's.
34 config XILINX_LL_TEMAC
35 tristate "Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver"
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| /openbmc/linux/Documentation/admin-guide/perf/ |
| H A D | imx-ddr.rst | 10 Selection of the value for each counter is done via the config registers. There
16 The "format" directory describes format of the config (event ID) and config1
17 (AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates
33 whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and
38 --AXI_ID defines AxID matching value.
[all …]
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| /openbmc/linux/drivers/net/ethernet/stmicro/stmmac/ |
| H A D | stmmac_platform.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 2007-2011 STMicroelectronics Ltd
26 * dwmac1000_validate_mcast_bins - validates the number of Multicast filter bins
57 * dwmac1000_validate_ucast_entries - validate the Unicast address entries
88 * stmmac_axi_setup - parse DT parameters for programming the AXI register
91 * if required, from device-tree the AXI internal register can be tuned
97 struct stmmac_axi *axi; in stmmac_axi_setup() local
99 np = of_parse_phandle(pdev->dev.of_node, "snps,axi-config", 0); in stmmac_axi_setup()
103 axi = devm_kzalloc(&pdev->dev, sizeof(*axi), GFP_KERNEL); in stmmac_axi_setup()
104 if (!axi) { in stmmac_axi_setup()
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/interconnect/ |
| H A D | qcom,rpm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPM Network-On-Chip Interconnect
10 - Georgi Djakov <georgi.djakov@linaro.org>
23 - qcom,msm8916-bimc
24 - qcom,msm8916-pcnoc
25 - qcom,msm8916-snoc
26 - qcom,msm8939-bimc
27 - qcom,msm8939-pcnoc
[all …]
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| H A D | qcom,sm8450-rpmh.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8450-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8450
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konrad.dybcio@linaro.org>
17 See also:: include/dt-bindings/interconnect/qcom,sm8450.h
22 - qcom,sm8450-aggre1-noc
23 - qcom,sm8450-aggre2-noc
[all …]
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| /openbmc/linux/drivers/fpga/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
15 config FPGA_MGR_SOCFPGA
21 config FPGA_MGR_SOCFPGA_A10
28 config ALTERA_PR_IP_CORE
33 config ALTERA_PR_IP_CORE_PLAT
40 config FPGA_MGR_ALTERA_PS_SPI
48 config FPGA_MGR_ALTERA_CVP
52 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
55 config FPGA_MGR_ZYNQ_FPGA
61 config FPGA_MGR_STRATIX10_SOC
[all …]
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| /openbmc/linux/drivers/clk/baikal-t1/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 config CLK_BAIKAL_T1
3 bool "Baikal-T1 Clocks Control Unit interface"
7 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
17 config CLK_BT1_CCU_PLL
18 bool "Baikal-T1 CCU PLLs support"
22 Enable this to support the PLLs embedded into the Baikal-T1 SoC
30 config CLK_BT1_CCU_DIV
31 bool "Baikal-T1 CCU Dividers support"
[all …]
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| /openbmc/u-boot/drivers/pci/ |
| H A D | Kconfig | 11 config DM_PCI
16 orgnising devices in U-Boot. For PCI, driver model keeps track of
20 config DM_PCI_COMPAT
29 config PCI_AARDVARK
39 config PCI_PNP
46 config PCIE_ASPEED
54 config PCIE_ECAM_GENERIC
55 bool "Generic ECAM-based PCI host controller support"
59 Say Y here if you want to enable support for generic ECAM-based
62 config PCIE_DW_MVEBU
[all …]
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| /openbmc/linux/arch/arc/plat-axs10x/ |
| H A D | axs10x.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
11 #include <asm/asm-offsets.h>
33 * --------------------- in axs10x_enable_gpio_intc_wire()
34 * | snps,arc700-intc | in axs10x_enable_gpio_intc_wire()
35 * --------------------- in axs10x_enable_gpio_intc_wire()
37 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
38 * | snps,dw-apb-gpio | | snps,dw-apb-gpio | in axs10x_enable_gpio_intc_wire()
39 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
43 * ------------------------ in axs10x_enable_gpio_intc_wire()
[all …]
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| /openbmc/u-boot/drivers/watchdog/ |
| H A D | Kconfig | 3 config WATCHDOG
4 bool "Enable U-Boot watchdog reset"
6 This option enables U-Boot watchdog support where U-Boot is using
7 watchdog_reset function to service watchdog device in U-Boot. Enable
8 this option if you want to service enabled watchdog by U-Boot. Disable
9 this option if you want U-Boot to start watchdog but never service it.
11 config HW_WATCHDOG
14 config WATCHDOG_RESET_DISABLE
18 that the watchdog will not be fed in u-boot.
20 config BCM2835_WDT
[all …]
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| /openbmc/linux/drivers/dma/xilinx/ |
| H A D | xilinx_dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
10 * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP
11 * core that provides high-bandwidth direct memory access between memory
12 * and AXI4-Stream type video target peripherals. The core provides efficient
18 * registers are accessed through an AXI4-Lite slave interface.
20 * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that
21 * provides high-bandwidth one dimensional direct memory access between memory
22 * and AXI4-Stream target peripherals. It supports one receive and one
25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | intel,dwmac-plat.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
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| H A D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | microchip,mpfs-clkcfg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daire McNamara <daire.mcnamara@microchip.com>
22 const: microchip,mpfs-clkcfg
26 - description: |
27 clock config registers:
29 axi, ahb and rtc/mtimer reference clocks as well as enable and reset
31 - description: |
[all …]
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| /openbmc/u-boot/drivers/fpga/ |
| H A D | socfpga_gen5.c | 1 // SPDX-License-Identifier: BSD-3-Clause
24 clrsetbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_set_cd_ratio()
35 msel = readl(&fpgamgr_regs->stat); in fpgamgr_program_init()
44 setbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_program_init()
59 clrbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_program_init()
75 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); in fpgamgr_program_init()
78 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); in fpgamgr_program_init()
81 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); in fpgamgr_program_init()
92 return -1; in fpgamgr_program_init()
96 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); in fpgamgr_program_init()
[all …]
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| /openbmc/linux/drivers/dma/dw-axi-dmac/ |
| H A D | dw-axi-dmac-platform.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
5 * Synopsys DesignWare AXI DMA Controller driver.
15 #include <linux/dma-mapping.h>
20 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include "dw-axi-dmac.h"
34 #include "../virt-dma.h"
37 * The set of bus widths supported by the DMA controller. DW AXI DMAC supports
38 * master data bus width up to 512 bits (for both AXI master interfaces), but
57 iowrite32(val, chip->regs + reg); in axi_dma_iowrite32()
[all …]
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