Lines Matching +full:axi +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
10 * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP
11 * core that provides high-bandwidth direct memory access between memory
12 * and AXI4-Stream type video target peripherals. The core provides efficient
18 * registers are accessed through an AXI4-Lite slave interface.
20 * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that
21 * provides high-bandwidth one dimensional direct memory access between memory
22 * and AXI4-Stream target peripherals. It supports one receive and one
25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
26 * Access (DMA) between a memory-mapped source address and a memory-mapped
29 * The AXI Multichannel Direct Memory Access (AXI MCDMA) core is a soft
30 * Xilinx IP that provides high-bandwidth direct memory access between
31 * memory and AXI4-Stream target peripherals. It provides scatter gather
50 #include <linux/io-64-nonatomic-lo-hi.h>
159 /* Axi VDMA Flush on Fsync bits */
167 /* AXI DMA Specific Registers/Offsets */
171 /* AXI DMA Specific Masks/Bit fields */
187 /* AXI CDMA Specific Registers/Offsets */
191 /* AXI CDMA Specific Masks */
197 /* AXI MCDMA Specific Registers/Offsets */
209 /* AXI MCDMA Specific Masks/Shifts */
222 * struct xilinx_vdma_desc_hw - Hardware Descriptor
243 * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA
252 * @app: APP Fields @0x20 - 0x30
267 * struct xilinx_aximcdma_desc_hw - Hardware Descriptor for AXI MCDMA
276 * @app: APP Fields @0x20 - 0x30
291 * struct xilinx_cdma_desc_hw - Hardware Descriptor
313 * struct xilinx_vdma_tx_segment - Descriptor segment
325 * struct xilinx_axidma_tx_segment - Descriptor segment
337 * struct xilinx_aximcdma_tx_segment - Descriptor segment
349 * struct xilinx_cdma_tx_segment - Descriptor segment
361 * struct xilinx_dma_tx_descriptor - Per Transaction structure
379 * struct xilinx_dma_chan - Driver specific DMA channel structure
402 * @config: Device configuration info
441 struct xilinx_vdma_config config; member
459 * enum xdma_ip_type - DMA IP type.
461 * @XDMA_TYPE_AXIDMA: Axi dma ip.
462 * @XDMA_TYPE_CDMA: Axi cdma ip.
463 * @XDMA_TYPE_VDMA: Axi vdma ip.
464 * @XDMA_TYPE_AXIMCDMA: Axi MCDMA ip.
484 * struct xilinx_dma_device - DMA device structure
492 * @dma_config: DMA config structure
493 * @axi_clk: DMA Axi4-lite interace clock
501 * @has_axistream_connected: AXI DMA connected to AXI Stream IP
529 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
535 return ioread32(chan->xdev->regs + reg); in dma_read()
540 iowrite32(value, chan->xdev->regs + reg); in dma_write()
546 dma_write(chan, chan->desc_offset + reg, value); in vdma_desc_write()
551 return dma_read(chan, chan->ctrl_offset + reg); in dma_ctrl_read()
557 dma_write(chan, chan->ctrl_offset + reg, value); in dma_ctrl_write()
573 * vdma_desc_write_64 - 64-bit descriptor write
587 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg); in vdma_desc_write_64()
590 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4); in vdma_desc_write_64()
595 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg); in dma_writeq()
601 if (chan->ext_addr) in xilinx_write()
612 if (chan->ext_addr) { in xilinx_axidma_buf()
613 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len); in xilinx_axidma_buf()
614 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used + in xilinx_axidma_buf()
617 hw->buf_addr = buf_addr + sg_used + period_len; in xilinx_axidma_buf()
625 if (chan->ext_addr) { in xilinx_aximcdma_buf()
626 hw->buf_addr = lower_32_bits(buf_addr + sg_used); in xilinx_aximcdma_buf()
627 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used); in xilinx_aximcdma_buf()
629 hw->buf_addr = buf_addr + sg_used; in xilinx_aximcdma_buf()
634 * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload length
647 seg = list_first_entry(&desc->segments, in xilinx_dma_get_metadata_ptr()
649 return seg->hw.app; in xilinx_dma_get_metadata_ptr()
656 /* -----------------------------------------------------------------------------
661 * xilinx_vdma_alloc_tx_segment - Allocate transaction segment
672 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); in xilinx_vdma_alloc_tx_segment()
676 segment->phys = phys; in xilinx_vdma_alloc_tx_segment()
682 * xilinx_cdma_alloc_tx_segment - Allocate transaction segment
693 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); in xilinx_cdma_alloc_tx_segment()
697 segment->phys = phys; in xilinx_cdma_alloc_tx_segment()
703 * xilinx_axidma_alloc_tx_segment - Allocate transaction segment
714 spin_lock_irqsave(&chan->lock, flags); in xilinx_axidma_alloc_tx_segment()
715 if (!list_empty(&chan->free_seg_list)) { in xilinx_axidma_alloc_tx_segment()
716 segment = list_first_entry(&chan->free_seg_list, in xilinx_axidma_alloc_tx_segment()
719 list_del(&segment->node); in xilinx_axidma_alloc_tx_segment()
721 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_axidma_alloc_tx_segment()
724 dev_dbg(chan->dev, "Could not find free tx segment\n"); in xilinx_axidma_alloc_tx_segment()
730 * xilinx_aximcdma_alloc_tx_segment - Allocate transaction segment
741 spin_lock_irqsave(&chan->lock, flags); in xilinx_aximcdma_alloc_tx_segment()
742 if (!list_empty(&chan->free_seg_list)) { in xilinx_aximcdma_alloc_tx_segment()
743 segment = list_first_entry(&chan->free_seg_list, in xilinx_aximcdma_alloc_tx_segment()
746 list_del(&segment->node); in xilinx_aximcdma_alloc_tx_segment()
748 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_aximcdma_alloc_tx_segment()
755 u32 next_desc = hw->next_desc; in xilinx_dma_clean_hw_desc()
756 u32 next_desc_msb = hw->next_desc_msb; in xilinx_dma_clean_hw_desc()
760 hw->next_desc = next_desc; in xilinx_dma_clean_hw_desc()
761 hw->next_desc_msb = next_desc_msb; in xilinx_dma_clean_hw_desc()
766 u32 next_desc = hw->next_desc; in xilinx_mcdma_clean_hw_desc()
767 u32 next_desc_msb = hw->next_desc_msb; in xilinx_mcdma_clean_hw_desc()
771 hw->next_desc = next_desc; in xilinx_mcdma_clean_hw_desc()
772 hw->next_desc_msb = next_desc_msb; in xilinx_mcdma_clean_hw_desc()
776 * xilinx_dma_free_tx_segment - Free transaction segment
783 xilinx_dma_clean_hw_desc(&segment->hw); in xilinx_dma_free_tx_segment()
785 list_add_tail(&segment->node, &chan->free_seg_list); in xilinx_dma_free_tx_segment()
789 * xilinx_mcdma_free_tx_segment - Free transaction segment
797 xilinx_mcdma_clean_hw_desc(&segment->hw); in xilinx_mcdma_free_tx_segment()
799 list_add_tail(&segment->node, &chan->free_seg_list); in xilinx_mcdma_free_tx_segment()
803 * xilinx_cdma_free_tx_segment - Free transaction segment
810 dma_pool_free(chan->desc_pool, segment, segment->phys); in xilinx_cdma_free_tx_segment()
814 * xilinx_vdma_free_tx_segment - Free transaction segment
821 dma_pool_free(chan->desc_pool, segment, segment->phys); in xilinx_vdma_free_tx_segment()
825 * xilinx_dma_alloc_tx_descriptor - Allocate transaction descriptor
839 INIT_LIST_HEAD(&desc->segments); in xilinx_dma_alloc_tx_descriptor()
845 * xilinx_dma_free_tx_descriptor - Free transaction descriptor
861 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in xilinx_dma_free_tx_descriptor()
862 list_for_each_entry_safe(segment, next, &desc->segments, node) { in xilinx_dma_free_tx_descriptor()
863 list_del(&segment->node); in xilinx_dma_free_tx_descriptor()
866 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_free_tx_descriptor()
868 &desc->segments, node) { in xilinx_dma_free_tx_descriptor()
869 list_del(&cdma_segment->node); in xilinx_dma_free_tx_descriptor()
872 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_free_tx_descriptor()
874 &desc->segments, node) { in xilinx_dma_free_tx_descriptor()
875 list_del(&axidma_segment->node); in xilinx_dma_free_tx_descriptor()
880 &desc->segments, node) { in xilinx_dma_free_tx_descriptor()
881 list_del(&aximcdma_segment->node); in xilinx_dma_free_tx_descriptor()
892 * xilinx_dma_free_desc_list - Free descriptors list
902 list_del(&desc->node); in xilinx_dma_free_desc_list()
908 * xilinx_dma_free_descriptors - Free channel descriptors
915 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_free_descriptors()
917 xilinx_dma_free_desc_list(chan, &chan->pending_list); in xilinx_dma_free_descriptors()
918 xilinx_dma_free_desc_list(chan, &chan->done_list); in xilinx_dma_free_descriptors()
919 xilinx_dma_free_desc_list(chan, &chan->active_list); in xilinx_dma_free_descriptors()
921 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_free_descriptors()
925 * xilinx_dma_free_chan_resources - Free channel resources
933 dev_dbg(chan->dev, "Free all channel resources.\n"); in xilinx_dma_free_chan_resources()
937 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_free_chan_resources()
938 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_free_chan_resources()
939 INIT_LIST_HEAD(&chan->free_seg_list); in xilinx_dma_free_chan_resources()
940 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_free_chan_resources()
943 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * in xilinx_dma_free_chan_resources()
944 XILINX_DMA_NUM_DESCS, chan->seg_v, in xilinx_dma_free_chan_resources()
945 chan->seg_p); in xilinx_dma_free_chan_resources()
948 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v), in xilinx_dma_free_chan_resources()
949 chan->cyclic_seg_v, chan->cyclic_seg_p); in xilinx_dma_free_chan_resources()
952 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { in xilinx_dma_free_chan_resources()
953 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_free_chan_resources()
954 INIT_LIST_HEAD(&chan->free_seg_list); in xilinx_dma_free_chan_resources()
955 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_free_chan_resources()
958 dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) * in xilinx_dma_free_chan_resources()
959 XILINX_DMA_NUM_DESCS, chan->seg_mv, in xilinx_dma_free_chan_resources()
960 chan->seg_p); in xilinx_dma_free_chan_resources()
963 if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA && in xilinx_dma_free_chan_resources()
964 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) { in xilinx_dma_free_chan_resources()
965 dma_pool_destroy(chan->desc_pool); in xilinx_dma_free_chan_resources()
966 chan->desc_pool = NULL; in xilinx_dma_free_chan_resources()
972 * xilinx_dma_get_residue - Compute residue for a given descriptor
990 list_for_each(entry, &desc->segments) { in xilinx_dma_get_residue()
991 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_get_residue()
995 cdma_hw = &cdma_seg->hw; in xilinx_dma_get_residue()
996 residue += (cdma_hw->control - cdma_hw->status) & in xilinx_dma_get_residue()
997 chan->xdev->max_buffer_len; in xilinx_dma_get_residue()
998 } else if (chan->xdev->dma_config->dmatype == in xilinx_dma_get_residue()
1003 axidma_hw = &axidma_seg->hw; in xilinx_dma_get_residue()
1004 residue += (axidma_hw->control - axidma_hw->status) & in xilinx_dma_get_residue()
1005 chan->xdev->max_buffer_len; in xilinx_dma_get_residue()
1011 aximcdma_hw = &aximcdma_seg->hw; in xilinx_dma_get_residue()
1013 (aximcdma_hw->control - aximcdma_hw->status) & in xilinx_dma_get_residue()
1014 chan->xdev->max_buffer_len; in xilinx_dma_get_residue()
1022 * xilinx_dma_chan_handle_cyclic - Cyclic dma callback
1033 dmaengine_desc_get_callback(&desc->async_tx, &cb); in xilinx_dma_chan_handle_cyclic()
1035 spin_unlock_irqrestore(&chan->lock, *flags); in xilinx_dma_chan_handle_cyclic()
1037 spin_lock_irqsave(&chan->lock, *flags); in xilinx_dma_chan_handle_cyclic()
1042 * xilinx_dma_chan_desc_cleanup - Clean channel descriptors
1050 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1052 list_for_each_entry_safe(desc, next, &chan->done_list, node) { in xilinx_dma_chan_desc_cleanup()
1055 if (desc->cyclic) { in xilinx_dma_chan_desc_cleanup()
1061 list_del(&desc->node); in xilinx_dma_chan_desc_cleanup()
1063 if (unlikely(desc->err)) { in xilinx_dma_chan_desc_cleanup()
1064 if (chan->direction == DMA_DEV_TO_MEM) in xilinx_dma_chan_desc_cleanup()
1072 result.residue = desc->residue; in xilinx_dma_chan_desc_cleanup()
1075 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1076 dmaengine_desc_get_callback_invoke(&desc->async_tx, &result); in xilinx_dma_chan_desc_cleanup()
1077 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1080 dma_run_dependencies(&desc->async_tx); in xilinx_dma_chan_desc_cleanup()
1087 if (chan->terminating) in xilinx_dma_chan_desc_cleanup()
1091 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1095 * xilinx_dma_do_tasklet - Schedule completion tasklet
1106 * xilinx_dma_alloc_chan_resources - Allocate channel resources
1117 if (chan->desc_pool) in xilinx_dma_alloc_chan_resources()
1124 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_alloc_chan_resources()
1126 chan->seg_v = dma_alloc_coherent(chan->dev, in xilinx_dma_alloc_chan_resources()
1127 sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS, in xilinx_dma_alloc_chan_resources()
1128 &chan->seg_p, GFP_KERNEL); in xilinx_dma_alloc_chan_resources()
1129 if (!chan->seg_v) { in xilinx_dma_alloc_chan_resources()
1130 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1132 chan->id); in xilinx_dma_alloc_chan_resources()
1133 return -ENOMEM; in xilinx_dma_alloc_chan_resources()
1141 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev, in xilinx_dma_alloc_chan_resources()
1142 sizeof(*chan->cyclic_seg_v), in xilinx_dma_alloc_chan_resources()
1143 &chan->cyclic_seg_p, in xilinx_dma_alloc_chan_resources()
1145 if (!chan->cyclic_seg_v) { in xilinx_dma_alloc_chan_resources()
1146 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1148 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * in xilinx_dma_alloc_chan_resources()
1149 XILINX_DMA_NUM_DESCS, chan->seg_v, in xilinx_dma_alloc_chan_resources()
1150 chan->seg_p); in xilinx_dma_alloc_chan_resources()
1151 return -ENOMEM; in xilinx_dma_alloc_chan_resources()
1153 chan->cyclic_seg_v->phys = chan->cyclic_seg_p; in xilinx_dma_alloc_chan_resources()
1156 chan->seg_v[i].hw.next_desc = in xilinx_dma_alloc_chan_resources()
1157 lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) * in xilinx_dma_alloc_chan_resources()
1159 chan->seg_v[i].hw.next_desc_msb = in xilinx_dma_alloc_chan_resources()
1160 upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) * in xilinx_dma_alloc_chan_resources()
1162 chan->seg_v[i].phys = chan->seg_p + in xilinx_dma_alloc_chan_resources()
1163 sizeof(*chan->seg_v) * i; in xilinx_dma_alloc_chan_resources()
1164 list_add_tail(&chan->seg_v[i].node, in xilinx_dma_alloc_chan_resources()
1165 &chan->free_seg_list); in xilinx_dma_alloc_chan_resources()
1167 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { in xilinx_dma_alloc_chan_resources()
1169 chan->seg_mv = dma_alloc_coherent(chan->dev, in xilinx_dma_alloc_chan_resources()
1170 sizeof(*chan->seg_mv) * in xilinx_dma_alloc_chan_resources()
1172 &chan->seg_p, GFP_KERNEL); in xilinx_dma_alloc_chan_resources()
1173 if (!chan->seg_mv) { in xilinx_dma_alloc_chan_resources()
1174 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1176 chan->id); in xilinx_dma_alloc_chan_resources()
1177 return -ENOMEM; in xilinx_dma_alloc_chan_resources()
1180 chan->seg_mv[i].hw.next_desc = in xilinx_dma_alloc_chan_resources()
1181 lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * in xilinx_dma_alloc_chan_resources()
1183 chan->seg_mv[i].hw.next_desc_msb = in xilinx_dma_alloc_chan_resources()
1184 upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * in xilinx_dma_alloc_chan_resources()
1186 chan->seg_mv[i].phys = chan->seg_p + in xilinx_dma_alloc_chan_resources()
1187 sizeof(*chan->seg_mv) * i; in xilinx_dma_alloc_chan_resources()
1188 list_add_tail(&chan->seg_mv[i].node, in xilinx_dma_alloc_chan_resources()
1189 &chan->free_seg_list); in xilinx_dma_alloc_chan_resources()
1191 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_alloc_chan_resources()
1192 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool", in xilinx_dma_alloc_chan_resources()
1193 chan->dev, in xilinx_dma_alloc_chan_resources()
1198 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool", in xilinx_dma_alloc_chan_resources()
1199 chan->dev, in xilinx_dma_alloc_chan_resources()
1205 if (!chan->desc_pool && in xilinx_dma_alloc_chan_resources()
1206 ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) && in xilinx_dma_alloc_chan_resources()
1207 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) { in xilinx_dma_alloc_chan_resources()
1208 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1210 chan->id); in xilinx_dma_alloc_chan_resources()
1211 return -ENOMEM; in xilinx_dma_alloc_chan_resources()
1216 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_alloc_chan_resources()
1217 /* For AXI DMA resetting once channel will reset the in xilinx_dma_alloc_chan_resources()
1224 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) in xilinx_dma_alloc_chan_resources()
1232 * xilinx_dma_calc_copysize - Calculate the amount of data to copy
1244 copy = min_t(size_t, size - done, in xilinx_dma_calc_copysize()
1245 chan->xdev->max_buffer_len); in xilinx_dma_calc_copysize()
1248 chan->xdev->common.copy_align) { in xilinx_dma_calc_copysize()
1254 (1 << chan->xdev->common.copy_align)); in xilinx_dma_calc_copysize()
1260 * xilinx_dma_tx_status - Get DMA transaction status
1281 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_tx_status()
1282 if (!list_empty(&chan->active_list)) { in xilinx_dma_tx_status()
1283 desc = list_last_entry(&chan->active_list, in xilinx_dma_tx_status()
1289 if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA) in xilinx_dma_tx_status()
1292 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_tx_status()
1300 * xilinx_dma_stop_transfer - Halt DMA channel
1318 * xilinx_cdma_stop_transfer - Wait for the current transfer to complete
1333 * xilinx_dma_start - Start DMA channel
1349 dev_err(chan->dev, "Cannot start channel %p: %x\n", in xilinx_dma_start()
1352 chan->err = true; in xilinx_dma_start()
1357 * xilinx_vdma_start_transfer - Starts VDMA transfer
1362 struct xilinx_vdma_config *config = &chan->config; in xilinx_vdma_start_transfer() local
1369 if (chan->err) in xilinx_vdma_start_transfer()
1372 if (!chan->idle) in xilinx_vdma_start_transfer()
1375 if (list_empty(&chan->pending_list)) in xilinx_vdma_start_transfer()
1378 desc = list_first_entry(&chan->pending_list, in xilinx_vdma_start_transfer()
1381 /* Configure the hardware using info in the config structure */ in xilinx_vdma_start_transfer()
1382 if (chan->has_vflip) { in xilinx_vdma_start_transfer()
1385 reg |= config->vflip_en; in xilinx_vdma_start_transfer()
1392 if (config->frm_cnt_en) in xilinx_vdma_start_transfer()
1398 if (config->park) in xilinx_vdma_start_transfer()
1405 j = chan->desc_submitcount; in xilinx_vdma_start_transfer()
1407 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_vdma_start_transfer()
1419 if (chan->err) in xilinx_vdma_start_transfer()
1423 if (chan->desc_submitcount < chan->num_frms) in xilinx_vdma_start_transfer()
1424 i = chan->desc_submitcount; in xilinx_vdma_start_transfer()
1426 list_for_each_entry(segment, &desc->segments, node) { in xilinx_vdma_start_transfer()
1427 if (chan->ext_addr) in xilinx_vdma_start_transfer()
1430 segment->hw.buf_addr, in xilinx_vdma_start_transfer()
1431 segment->hw.buf_addr_msb); in xilinx_vdma_start_transfer()
1435 segment->hw.buf_addr); in xilinx_vdma_start_transfer()
1444 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); in xilinx_vdma_start_transfer()
1446 last->hw.stride); in xilinx_vdma_start_transfer()
1447 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); in xilinx_vdma_start_transfer()
1449 chan->desc_submitcount++; in xilinx_vdma_start_transfer()
1450 chan->desc_pendingcount--; in xilinx_vdma_start_transfer()
1451 list_move_tail(&desc->node, &chan->active_list); in xilinx_vdma_start_transfer()
1452 if (chan->desc_submitcount == chan->num_frms) in xilinx_vdma_start_transfer()
1453 chan->desc_submitcount = 0; in xilinx_vdma_start_transfer()
1455 chan->idle = false; in xilinx_vdma_start_transfer()
1459 * xilinx_cdma_start_transfer - Starts cdma transfer
1468 if (chan->err) in xilinx_cdma_start_transfer()
1471 if (!chan->idle) in xilinx_cdma_start_transfer()
1474 if (list_empty(&chan->pending_list)) in xilinx_cdma_start_transfer()
1477 head_desc = list_first_entry(&chan->pending_list, in xilinx_cdma_start_transfer()
1479 tail_desc = list_last_entry(&chan->pending_list, in xilinx_cdma_start_transfer()
1481 tail_segment = list_last_entry(&tail_desc->segments, in xilinx_cdma_start_transfer()
1484 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { in xilinx_cdma_start_transfer()
1486 ctrl_reg |= chan->desc_pendingcount << in xilinx_cdma_start_transfer()
1491 if (chan->has_sg) { in xilinx_cdma_start_transfer()
1499 head_desc->async_tx.phys); in xilinx_cdma_start_transfer()
1503 tail_segment->phys); in xilinx_cdma_start_transfer()
1509 segment = list_first_entry(&head_desc->segments, in xilinx_cdma_start_transfer()
1513 hw = &segment->hw; in xilinx_cdma_start_transfer()
1516 xilinx_prep_dma_addr_t(hw->src_addr)); in xilinx_cdma_start_transfer()
1518 xilinx_prep_dma_addr_t(hw->dest_addr)); in xilinx_cdma_start_transfer()
1522 hw->control & chan->xdev->max_buffer_len); in xilinx_cdma_start_transfer()
1525 list_splice_tail_init(&chan->pending_list, &chan->active_list); in xilinx_cdma_start_transfer()
1526 chan->desc_pendingcount = 0; in xilinx_cdma_start_transfer()
1527 chan->idle = false; in xilinx_cdma_start_transfer()
1531 * xilinx_dma_start_transfer - Starts DMA transfer
1540 if (chan->err) in xilinx_dma_start_transfer()
1543 if (list_empty(&chan->pending_list)) in xilinx_dma_start_transfer()
1546 if (!chan->idle) in xilinx_dma_start_transfer()
1549 head_desc = list_first_entry(&chan->pending_list, in xilinx_dma_start_transfer()
1551 tail_desc = list_last_entry(&chan->pending_list, in xilinx_dma_start_transfer()
1553 tail_segment = list_last_entry(&tail_desc->segments, in xilinx_dma_start_transfer()
1558 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { in xilinx_dma_start_transfer()
1560 reg |= chan->desc_pendingcount << in xilinx_dma_start_transfer()
1565 if (chan->has_sg) in xilinx_dma_start_transfer()
1567 head_desc->async_tx.phys); in xilinx_dma_start_transfer()
1569 reg |= chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT; in xilinx_dma_start_transfer()
1574 if (chan->err) in xilinx_dma_start_transfer()
1578 if (chan->has_sg) { in xilinx_dma_start_transfer()
1579 if (chan->cyclic) in xilinx_dma_start_transfer()
1581 chan->cyclic_seg_v->phys); in xilinx_dma_start_transfer()
1584 tail_segment->phys); in xilinx_dma_start_transfer()
1589 segment = list_first_entry(&head_desc->segments, in xilinx_dma_start_transfer()
1592 hw = &segment->hw; in xilinx_dma_start_transfer()
1595 xilinx_prep_dma_addr_t(hw->buf_addr)); in xilinx_dma_start_transfer()
1599 hw->control & chan->xdev->max_buffer_len); in xilinx_dma_start_transfer()
1602 list_splice_tail_init(&chan->pending_list, &chan->active_list); in xilinx_dma_start_transfer()
1603 chan->desc_pendingcount = 0; in xilinx_dma_start_transfer()
1604 chan->idle = false; in xilinx_dma_start_transfer()
1608 * xilinx_mcdma_start_transfer - Starts MCDMA transfer
1622 if (chan->err) in xilinx_mcdma_start_transfer()
1625 if (!chan->idle) in xilinx_mcdma_start_transfer()
1628 if (list_empty(&chan->pending_list)) in xilinx_mcdma_start_transfer()
1631 head_desc = list_first_entry(&chan->pending_list, in xilinx_mcdma_start_transfer()
1633 tail_desc = list_last_entry(&chan->pending_list, in xilinx_mcdma_start_transfer()
1635 tail_segment = list_last_entry(&tail_desc->segments, in xilinx_mcdma_start_transfer()
1638 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); in xilinx_mcdma_start_transfer()
1640 if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) { in xilinx_mcdma_start_transfer()
1642 reg |= chan->desc_pendingcount << in xilinx_mcdma_start_transfer()
1647 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); in xilinx_mcdma_start_transfer()
1650 xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest), in xilinx_mcdma_start_transfer()
1651 head_desc->async_tx.phys); in xilinx_mcdma_start_transfer()
1655 reg |= BIT(chan->tdest); in xilinx_mcdma_start_transfer()
1659 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); in xilinx_mcdma_start_transfer()
1661 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); in xilinx_mcdma_start_transfer()
1665 if (chan->err) in xilinx_mcdma_start_transfer()
1669 xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest), in xilinx_mcdma_start_transfer()
1670 tail_segment->phys); in xilinx_mcdma_start_transfer()
1672 list_splice_tail_init(&chan->pending_list, &chan->active_list); in xilinx_mcdma_start_transfer()
1673 chan->desc_pendingcount = 0; in xilinx_mcdma_start_transfer()
1674 chan->idle = false; in xilinx_mcdma_start_transfer()
1678 * xilinx_dma_issue_pending - Issue pending transactions
1686 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_issue_pending()
1687 chan->start_transfer(chan); in xilinx_dma_issue_pending()
1688 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_issue_pending()
1692 * xilinx_dma_device_config - Configure the DMA channel
1694 * @config: channel configuration
1699 struct dma_slave_config *config) in xilinx_dma_device_config() argument
1705 * xilinx_dma_complete_descriptor - Mark the active descriptor as complete
1715 if (list_empty(&chan->active_list)) in xilinx_dma_complete_descriptor()
1718 list_for_each_entry_safe(desc, next, &chan->active_list, node) { in xilinx_dma_complete_descriptor()
1719 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_complete_descriptor()
1722 seg = list_last_entry(&desc->segments, in xilinx_dma_complete_descriptor()
1724 if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg) in xilinx_dma_complete_descriptor()
1727 if (chan->has_sg && chan->xdev->dma_config->dmatype != in xilinx_dma_complete_descriptor()
1729 desc->residue = xilinx_dma_get_residue(chan, desc); in xilinx_dma_complete_descriptor()
1731 desc->residue = 0; in xilinx_dma_complete_descriptor()
1732 desc->err = chan->err; in xilinx_dma_complete_descriptor()
1734 list_del(&desc->node); in xilinx_dma_complete_descriptor()
1735 if (!desc->cyclic) in xilinx_dma_complete_descriptor()
1736 dma_cookie_complete(&desc->async_tx); in xilinx_dma_complete_descriptor()
1737 list_add_tail(&desc->node, &chan->done_list); in xilinx_dma_complete_descriptor()
1742 * xilinx_dma_reset - Reset DMA channel
1760 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n", in xilinx_dma_reset()
1763 return -ETIMEDOUT; in xilinx_dma_reset()
1766 chan->err = false; in xilinx_dma_reset()
1767 chan->idle = true; in xilinx_dma_reset()
1768 chan->desc_pendingcount = 0; in xilinx_dma_reset()
1769 chan->desc_submitcount = 0; in xilinx_dma_reset()
1775 * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts
1797 * xilinx_mcdma_irq_handler - MCDMA Interrupt handler
1808 if (chan->direction == DMA_DEV_TO_MEM) in xilinx_mcdma_irq_handler()
1820 if (chan->direction == DMA_DEV_TO_MEM) in xilinx_mcdma_irq_handler()
1821 chan_offset = chan->xdev->dma_config->max_channels / 2; in xilinx_mcdma_irq_handler()
1823 chan_offset = chan_offset + (chan_id - 1); in xilinx_mcdma_irq_handler()
1824 chan = chan->xdev->chan[chan_offset]; in xilinx_mcdma_irq_handler()
1826 status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest)); in xilinx_mcdma_irq_handler()
1830 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest), in xilinx_mcdma_irq_handler()
1834 dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n", in xilinx_mcdma_irq_handler()
1838 (chan->tdest)), in xilinx_mcdma_irq_handler()
1840 (chan->tdest))); in xilinx_mcdma_irq_handler()
1841 chan->err = true; in xilinx_mcdma_irq_handler()
1849 dev_dbg(chan->dev, "Inter-packet latency too long\n"); in xilinx_mcdma_irq_handler()
1853 spin_lock(&chan->lock); in xilinx_mcdma_irq_handler()
1855 chan->idle = true; in xilinx_mcdma_irq_handler()
1856 chan->start_transfer(chan); in xilinx_mcdma_irq_handler()
1857 spin_unlock(&chan->lock); in xilinx_mcdma_irq_handler()
1860 tasklet_hi_schedule(&chan->tasklet); in xilinx_mcdma_irq_handler()
1865 * xilinx_dma_irq_handler - DMA Interrupt handler
1897 if (!chan->flush_on_fsync || in xilinx_dma_irq_handler()
1899 dev_err(chan->dev, in xilinx_dma_irq_handler()
1904 chan->err = true; in xilinx_dma_irq_handler()
1910 spin_lock(&chan->lock); in xilinx_dma_irq_handler()
1912 chan->idle = true; in xilinx_dma_irq_handler()
1913 chan->start_transfer(chan); in xilinx_dma_irq_handler()
1914 spin_unlock(&chan->lock); in xilinx_dma_irq_handler()
1917 tasklet_schedule(&chan->tasklet); in xilinx_dma_irq_handler()
1922 * append_desc_queue - Queuing descriptor
1935 if (list_empty(&chan->pending_list)) in append_desc_queue()
1942 tail_desc = list_last_entry(&chan->pending_list, in append_desc_queue()
1944 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in append_desc_queue()
1945 tail_segment = list_last_entry(&tail_desc->segments, in append_desc_queue()
1948 tail_segment->hw.next_desc = (u32)desc->async_tx.phys; in append_desc_queue()
1949 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in append_desc_queue()
1950 cdma_tail_segment = list_last_entry(&tail_desc->segments, in append_desc_queue()
1953 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; in append_desc_queue()
1954 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in append_desc_queue()
1955 axidma_tail_segment = list_last_entry(&tail_desc->segments, in append_desc_queue()
1958 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; in append_desc_queue()
1961 list_last_entry(&tail_desc->segments, in append_desc_queue()
1964 aximcdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; in append_desc_queue()
1972 list_add_tail(&desc->node, &chan->pending_list); in append_desc_queue()
1973 chan->desc_pendingcount++; in append_desc_queue()
1975 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) in append_desc_queue()
1976 && unlikely(chan->desc_pendingcount > chan->num_frms)) { in append_desc_queue()
1977 dev_dbg(chan->dev, "desc pendingcount is too high\n"); in append_desc_queue()
1978 chan->desc_pendingcount = chan->num_frms; in append_desc_queue()
1983 * xilinx_dma_tx_submit - Submit DMA transaction
1991 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan); in xilinx_dma_tx_submit()
1996 if (chan->cyclic) { in xilinx_dma_tx_submit()
1998 return -EBUSY; in xilinx_dma_tx_submit()
2001 if (chan->err) { in xilinx_dma_tx_submit()
2011 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_tx_submit()
2018 if (desc->cyclic) in xilinx_dma_tx_submit()
2019 chan->cyclic = true; in xilinx_dma_tx_submit()
2021 chan->terminating = false; in xilinx_dma_tx_submit()
2023 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_tx_submit()
2029 * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a
2047 if (!is_slave_direction(xt->dir)) in xilinx_vdma_dma_prep_interleaved()
2050 if (!xt->numf || !xt->sgl[0].size) in xilinx_vdma_dma_prep_interleaved()
2053 if (xt->frame_size != 1) in xilinx_vdma_dma_prep_interleaved()
2061 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_vdma_dma_prep_interleaved()
2062 desc->async_tx.tx_submit = xilinx_dma_tx_submit; in xilinx_vdma_dma_prep_interleaved()
2063 async_tx_ack(&desc->async_tx); in xilinx_vdma_dma_prep_interleaved()
2071 hw = &segment->hw; in xilinx_vdma_dma_prep_interleaved()
2072 hw->vsize = xt->numf; in xilinx_vdma_dma_prep_interleaved()
2073 hw->hsize = xt->sgl[0].size; in xilinx_vdma_dma_prep_interleaved()
2074 hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) << in xilinx_vdma_dma_prep_interleaved()
2076 hw->stride |= chan->config.frm_dly << in xilinx_vdma_dma_prep_interleaved()
2079 if (xt->dir != DMA_MEM_TO_DEV) { in xilinx_vdma_dma_prep_interleaved()
2080 if (chan->ext_addr) { in xilinx_vdma_dma_prep_interleaved()
2081 hw->buf_addr = lower_32_bits(xt->dst_start); in xilinx_vdma_dma_prep_interleaved()
2082 hw->buf_addr_msb = upper_32_bits(xt->dst_start); in xilinx_vdma_dma_prep_interleaved()
2084 hw->buf_addr = xt->dst_start; in xilinx_vdma_dma_prep_interleaved()
2087 if (chan->ext_addr) { in xilinx_vdma_dma_prep_interleaved()
2088 hw->buf_addr = lower_32_bits(xt->src_start); in xilinx_vdma_dma_prep_interleaved()
2089 hw->buf_addr_msb = upper_32_bits(xt->src_start); in xilinx_vdma_dma_prep_interleaved()
2091 hw->buf_addr = xt->src_start; in xilinx_vdma_dma_prep_interleaved()
2096 list_add_tail(&segment->node, &desc->segments); in xilinx_vdma_dma_prep_interleaved()
2099 segment = list_first_entry(&desc->segments, in xilinx_vdma_dma_prep_interleaved()
2101 desc->async_tx.phys = segment->phys; in xilinx_vdma_dma_prep_interleaved()
2103 return &desc->async_tx; in xilinx_vdma_dma_prep_interleaved()
2111 * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction
2129 if (!len || len > chan->xdev->max_buffer_len) in xilinx_cdma_prep_memcpy()
2136 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_cdma_prep_memcpy()
2137 desc->async_tx.tx_submit = xilinx_dma_tx_submit; in xilinx_cdma_prep_memcpy()
2144 hw = &segment->hw; in xilinx_cdma_prep_memcpy()
2145 hw->control = len; in xilinx_cdma_prep_memcpy()
2146 hw->src_addr = dma_src; in xilinx_cdma_prep_memcpy()
2147 hw->dest_addr = dma_dst; in xilinx_cdma_prep_memcpy()
2148 if (chan->ext_addr) { in xilinx_cdma_prep_memcpy()
2149 hw->src_addr_msb = upper_32_bits(dma_src); in xilinx_cdma_prep_memcpy()
2150 hw->dest_addr_msb = upper_32_bits(dma_dst); in xilinx_cdma_prep_memcpy()
2154 list_add_tail(&segment->node, &desc->segments); in xilinx_cdma_prep_memcpy()
2156 desc->async_tx.phys = segment->phys; in xilinx_cdma_prep_memcpy()
2157 hw->next_desc = segment->phys; in xilinx_cdma_prep_memcpy()
2159 return &desc->async_tx; in xilinx_cdma_prep_memcpy()
2167 * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
2199 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_dma_prep_slave_sg()
2200 desc->async_tx.tx_submit = xilinx_dma_tx_submit; in xilinx_dma_prep_slave_sg()
2221 hw = &segment->hw; in xilinx_dma_prep_slave_sg()
2227 hw->control = copy; in xilinx_dma_prep_slave_sg()
2229 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_dma_prep_slave_sg()
2231 memcpy(hw->app, app_w, sizeof(u32) * in xilinx_dma_prep_slave_sg()
2241 list_add_tail(&segment->node, &desc->segments); in xilinx_dma_prep_slave_sg()
2245 segment = list_first_entry(&desc->segments, in xilinx_dma_prep_slave_sg()
2247 desc->async_tx.phys = segment->phys; in xilinx_dma_prep_slave_sg()
2250 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_dma_prep_slave_sg()
2251 segment->hw.control |= XILINX_DMA_BD_SOP; in xilinx_dma_prep_slave_sg()
2252 segment = list_last_entry(&desc->segments, in xilinx_dma_prep_slave_sg()
2255 segment->hw.control |= XILINX_DMA_BD_EOP; in xilinx_dma_prep_slave_sg()
2258 if (chan->xdev->has_axistream_connected) in xilinx_dma_prep_slave_sg()
2259 desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops; in xilinx_dma_prep_slave_sg()
2261 return &desc->async_tx; in xilinx_dma_prep_slave_sg()
2269 * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction
2308 chan->direction = direction; in xilinx_dma_prep_dma_cyclic()
2309 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_dma_prep_dma_cyclic()
2310 desc->async_tx.tx_submit = xilinx_dma_tx_submit; in xilinx_dma_prep_dma_cyclic()
2329 hw = &segment->hw; in xilinx_dma_prep_dma_cyclic()
2332 hw->control = copy; in xilinx_dma_prep_dma_cyclic()
2335 prev->hw.next_desc = segment->phys; in xilinx_dma_prep_dma_cyclic()
2344 list_add_tail(&segment->node, &desc->segments); in xilinx_dma_prep_dma_cyclic()
2348 head_segment = list_first_entry(&desc->segments, in xilinx_dma_prep_dma_cyclic()
2350 desc->async_tx.phys = head_segment->phys; in xilinx_dma_prep_dma_cyclic()
2352 desc->cyclic = true; in xilinx_dma_prep_dma_cyclic()
2357 segment = list_last_entry(&desc->segments, in xilinx_dma_prep_dma_cyclic()
2360 segment->hw.next_desc = (u32) head_segment->phys; in xilinx_dma_prep_dma_cyclic()
2364 head_segment->hw.control |= XILINX_DMA_BD_SOP; in xilinx_dma_prep_dma_cyclic()
2365 segment->hw.control |= XILINX_DMA_BD_EOP; in xilinx_dma_prep_dma_cyclic()
2368 return &desc->async_tx; in xilinx_dma_prep_dma_cyclic()
2376 * xilinx_mcdma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
2409 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_mcdma_prep_slave_sg()
2410 desc->async_tx.tx_submit = xilinx_dma_tx_submit; in xilinx_mcdma_prep_slave_sg()
2429 copy = min_t(size_t, sg_dma_len(sg) - sg_used, in xilinx_mcdma_prep_slave_sg()
2430 chan->xdev->max_buffer_len); in xilinx_mcdma_prep_slave_sg()
2431 hw = &segment->hw; in xilinx_mcdma_prep_slave_sg()
2436 hw->control = copy; in xilinx_mcdma_prep_slave_sg()
2438 if (chan->direction == DMA_MEM_TO_DEV && app_w) { in xilinx_mcdma_prep_slave_sg()
2439 memcpy(hw->app, app_w, sizeof(u32) * in xilinx_mcdma_prep_slave_sg()
2448 list_add_tail(&segment->node, &desc->segments); in xilinx_mcdma_prep_slave_sg()
2452 segment = list_first_entry(&desc->segments, in xilinx_mcdma_prep_slave_sg()
2454 desc->async_tx.phys = segment->phys; in xilinx_mcdma_prep_slave_sg()
2457 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_mcdma_prep_slave_sg()
2458 segment->hw.control |= XILINX_MCDMA_BD_SOP; in xilinx_mcdma_prep_slave_sg()
2459 segment = list_last_entry(&desc->segments, in xilinx_mcdma_prep_slave_sg()
2462 segment->hw.control |= XILINX_MCDMA_BD_EOP; in xilinx_mcdma_prep_slave_sg()
2465 return &desc->async_tx; in xilinx_mcdma_prep_slave_sg()
2474 * xilinx_dma_terminate_all - Halt the channel and free descriptors
2485 if (!chan->cyclic) { in xilinx_dma_terminate_all()
2486 err = chan->stop_transfer(chan); in xilinx_dma_terminate_all()
2488 dev_err(chan->dev, "Cannot stop channel %p: %x\n", in xilinx_dma_terminate_all()
2491 chan->err = true; in xilinx_dma_terminate_all()
2497 chan->terminating = true; in xilinx_dma_terminate_all()
2499 chan->idle = true; in xilinx_dma_terminate_all()
2501 if (chan->cyclic) { in xilinx_dma_terminate_all()
2505 chan->cyclic = false; in xilinx_dma_terminate_all()
2508 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) in xilinx_dma_terminate_all()
2519 tasklet_kill(&chan->tasklet); in xilinx_dma_synchronize()
2523 * xilinx_vdma_channel_set_config - Configure VDMA channel
2524 * Run-time configuration for Axi VDMA, supports:
2526 * . configure interrupt coalescing and inter-packet delay threshold
2541 if (cfg->reset) in xilinx_vdma_channel_set_config()
2546 chan->config.frm_dly = cfg->frm_dly; in xilinx_vdma_channel_set_config()
2547 chan->config.park = cfg->park; in xilinx_vdma_channel_set_config()
2550 chan->config.gen_lock = cfg->gen_lock; in xilinx_vdma_channel_set_config()
2551 chan->config.master = cfg->master; in xilinx_vdma_channel_set_config()
2554 if (cfg->gen_lock && chan->genlock) { in xilinx_vdma_channel_set_config()
2557 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT; in xilinx_vdma_channel_set_config()
2560 chan->config.frm_cnt_en = cfg->frm_cnt_en; in xilinx_vdma_channel_set_config()
2561 chan->config.vflip_en = cfg->vflip_en; in xilinx_vdma_channel_set_config()
2563 if (cfg->park) in xilinx_vdma_channel_set_config()
2564 chan->config.park_frm = cfg->park_frm; in xilinx_vdma_channel_set_config()
2566 chan->config.park_frm = -1; in xilinx_vdma_channel_set_config()
2568 chan->config.coalesc = cfg->coalesc; in xilinx_vdma_channel_set_config()
2569 chan->config.delay = cfg->delay; in xilinx_vdma_channel_set_config()
2571 if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) { in xilinx_vdma_channel_set_config()
2573 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT; in xilinx_vdma_channel_set_config()
2574 chan->config.coalesc = cfg->coalesc; in xilinx_vdma_channel_set_config()
2577 if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) { in xilinx_vdma_channel_set_config()
2579 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT; in xilinx_vdma_channel_set_config()
2580 chan->config.delay = cfg->delay; in xilinx_vdma_channel_set_config()
2585 dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT; in xilinx_vdma_channel_set_config()
2593 /* -----------------------------------------------------------------------------
2598 * xilinx_dma_chan_remove - Per Channel remove function
2607 if (chan->irq > 0) in xilinx_dma_chan_remove()
2608 free_irq(chan->irq, chan); in xilinx_dma_chan_remove()
2610 tasklet_kill(&chan->tasklet); in xilinx_dma_chan_remove()
2612 list_del(&chan->common.device_node); in xilinx_dma_chan_remove()
2623 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); in axidma_clk_init()
2625 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); in axidma_clk_init()
2627 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); in axidma_clk_init()
2631 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); in axidma_clk_init()
2635 *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk"); in axidma_clk_init()
2641 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err); in axidma_clk_init()
2647 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); in axidma_clk_init()
2653 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); in axidma_clk_init()
2659 dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err); in axidma_clk_init()
2685 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); in axicdma_clk_init()
2687 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); in axicdma_clk_init()
2689 *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk"); in axicdma_clk_init()
2691 return dev_err_probe(&pdev->dev, PTR_ERR(*dev_clk), "failed to get dev_clk\n"); in axicdma_clk_init()
2695 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err); in axicdma_clk_init()
2701 dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err); in axicdma_clk_init()
2719 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); in axivdma_clk_init()
2721 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); in axivdma_clk_init()
2723 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); in axivdma_clk_init()
2727 *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk"); in axivdma_clk_init()
2731 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); in axivdma_clk_init()
2735 *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk"); in axivdma_clk_init()
2741 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", in axivdma_clk_init()
2748 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); in axivdma_clk_init()
2754 dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err); in axivdma_clk_init()
2760 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); in axivdma_clk_init()
2766 dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err); in axivdma_clk_init()
2786 clk_disable_unprepare(xdev->rxs_clk); in xdma_disable_allclks()
2787 clk_disable_unprepare(xdev->rx_clk); in xdma_disable_allclks()
2788 clk_disable_unprepare(xdev->txs_clk); in xdma_disable_allclks()
2789 clk_disable_unprepare(xdev->tx_clk); in xdma_disable_allclks()
2790 clk_disable_unprepare(xdev->axi_clk); in xdma_disable_allclks()
2794 * xilinx_dma_chan_probe - Per Channel Probing
2812 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); in xilinx_dma_chan_probe()
2814 return -ENOMEM; in xilinx_dma_chan_probe()
2816 chan->dev = xdev->dev; in xilinx_dma_chan_probe()
2817 chan->xdev = xdev; in xilinx_dma_chan_probe()
2818 chan->desc_pendingcount = 0x0; in xilinx_dma_chan_probe()
2819 chan->ext_addr = xdev->ext_addr; in xilinx_dma_chan_probe()
2825 chan->idle = true; in xilinx_dma_chan_probe()
2827 spin_lock_init(&chan->lock); in xilinx_dma_chan_probe()
2828 INIT_LIST_HEAD(&chan->pending_list); in xilinx_dma_chan_probe()
2829 INIT_LIST_HEAD(&chan->done_list); in xilinx_dma_chan_probe()
2830 INIT_LIST_HEAD(&chan->active_list); in xilinx_dma_chan_probe()
2831 INIT_LIST_HEAD(&chan->free_seg_list); in xilinx_dma_chan_probe()
2834 has_dre = of_property_read_bool(node, "xlnx,include-dre"); in xilinx_dma_chan_probe()
2836 of_property_read_u8(node, "xlnx,irq-delay", &chan->irq_delay); in xilinx_dma_chan_probe()
2838 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode"); in xilinx_dma_chan_probe()
2842 dev_err(xdev->dev, "missing xlnx,datawidth property\n"); in xilinx_dma_chan_probe()
2852 xdev->common.copy_align = (enum dmaengine_alignment)fls(width - 1); in xilinx_dma_chan_probe()
2854 if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") || in xilinx_dma_chan_probe()
2855 of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") || in xilinx_dma_chan_probe()
2856 of_device_is_compatible(node, "xlnx,axi-cdma-channel")) { in xilinx_dma_chan_probe()
2857 chan->direction = DMA_MEM_TO_DEV; in xilinx_dma_chan_probe()
2858 chan->id = xdev->mm2s_chan_id++; in xilinx_dma_chan_probe()
2859 chan->tdest = chan->id; in xilinx_dma_chan_probe()
2861 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; in xilinx_dma_chan_probe()
2862 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in xilinx_dma_chan_probe()
2863 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET; in xilinx_dma_chan_probe()
2864 chan->config.park = 1; in xilinx_dma_chan_probe()
2866 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || in xilinx_dma_chan_probe()
2867 xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S) in xilinx_dma_chan_probe()
2868 chan->flush_on_fsync = true; in xilinx_dma_chan_probe()
2871 "xlnx,axi-vdma-s2mm-channel") || in xilinx_dma_chan_probe()
2873 "xlnx,axi-dma-s2mm-channel")) { in xilinx_dma_chan_probe()
2874 chan->direction = DMA_DEV_TO_MEM; in xilinx_dma_chan_probe()
2875 chan->id = xdev->s2mm_chan_id++; in xilinx_dma_chan_probe()
2876 chan->tdest = chan->id - xdev->dma_config->max_channels / 2; in xilinx_dma_chan_probe()
2877 chan->has_vflip = of_property_read_bool(node, in xilinx_dma_chan_probe()
2878 "xlnx,enable-vert-flip"); in xilinx_dma_chan_probe()
2879 if (chan->has_vflip) { in xilinx_dma_chan_probe()
2880 chan->config.vflip_en = dma_read(chan, in xilinx_dma_chan_probe()
2885 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) in xilinx_dma_chan_probe()
2886 chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET; in xilinx_dma_chan_probe()
2888 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; in xilinx_dma_chan_probe()
2890 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in xilinx_dma_chan_probe()
2891 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET; in xilinx_dma_chan_probe()
2892 chan->config.park = 1; in xilinx_dma_chan_probe()
2894 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || in xilinx_dma_chan_probe()
2895 xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM) in xilinx_dma_chan_probe()
2896 chan->flush_on_fsync = true; in xilinx_dma_chan_probe()
2899 dev_err(xdev->dev, "Invalid channel compatible node\n"); in xilinx_dma_chan_probe()
2900 return -EINVAL; in xilinx_dma_chan_probe()
2904 chan->irq = of_irq_get(node, chan->tdest); in xilinx_dma_chan_probe()
2905 if (chan->irq < 0) in xilinx_dma_chan_probe()
2906 return dev_err_probe(xdev->dev, chan->irq, "failed to get irq\n"); in xilinx_dma_chan_probe()
2907 err = request_irq(chan->irq, xdev->dma_config->irq_handler, in xilinx_dma_chan_probe()
2908 IRQF_SHARED, "xilinx-dma-controller", chan); in xilinx_dma_chan_probe()
2910 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq); in xilinx_dma_chan_probe()
2914 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_chan_probe()
2915 chan->start_transfer = xilinx_dma_start_transfer; in xilinx_dma_chan_probe()
2916 chan->stop_transfer = xilinx_dma_stop_transfer; in xilinx_dma_chan_probe()
2917 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { in xilinx_dma_chan_probe()
2918 chan->start_transfer = xilinx_mcdma_start_transfer; in xilinx_dma_chan_probe()
2919 chan->stop_transfer = xilinx_dma_stop_transfer; in xilinx_dma_chan_probe()
2920 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_chan_probe()
2921 chan->start_transfer = xilinx_cdma_start_transfer; in xilinx_dma_chan_probe()
2922 chan->stop_transfer = xilinx_cdma_stop_transfer; in xilinx_dma_chan_probe()
2924 chan->start_transfer = xilinx_vdma_start_transfer; in xilinx_dma_chan_probe()
2925 chan->stop_transfer = xilinx_dma_stop_transfer; in xilinx_dma_chan_probe()
2929 if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) { in xilinx_dma_chan_probe()
2930 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA || in xilinx_dma_chan_probe()
2933 chan->has_sg = true; in xilinx_dma_chan_probe()
2934 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id, in xilinx_dma_chan_probe()
2935 chan->has_sg ? "enabled" : "disabled"); in xilinx_dma_chan_probe()
2939 tasklet_setup(&chan->tasklet, xilinx_dma_do_tasklet); in xilinx_dma_chan_probe()
2945 chan->common.device = &xdev->common; in xilinx_dma_chan_probe()
2947 list_add_tail(&chan->common.device_node, &xdev->common.channels); in xilinx_dma_chan_probe()
2948 xdev->chan[chan->id] = chan; in xilinx_dma_chan_probe()
2953 dev_err(xdev->dev, "Reset channel failed\n"); in xilinx_dma_chan_probe()
2961 * xilinx_dma_child_probe - Per child node probe
2962 * It get number of dma-channels per child node from
2963 * device-tree and initializes all the channels.
2976 ret = of_property_read_u32(node, "dma-channels", &nr_channels); in xilinx_dma_child_probe()
2977 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA && ret < 0) in xilinx_dma_child_probe()
2978 dev_warn(xdev->dev, "missing dma-channels property\n"); in xilinx_dma_child_probe()
2990 * of_dma_xilinx_xlate - Translation function
2999 struct xilinx_dma_device *xdev = ofdma->of_dma_data; in of_dma_xilinx_xlate()
3000 int chan_id = dma_spec->args[0]; in of_dma_xilinx_xlate()
3002 if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id]) in of_dma_xilinx_xlate()
3005 return dma_get_slave_channel(&xdev->chan[chan_id]->common); in of_dma_xilinx_xlate()
3036 { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config },
3037 { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config },
3038 { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config },
3039 { .compatible = "xlnx,axi-mcdma-1.00.a", .data = &aximcdma_config },
3045 * xilinx_dma_probe - Driver probe function
3055 struct device_node *node = pdev->dev.of_node; in xilinx_dma_probe()
3057 struct device_node *child, *np = pdev->dev.of_node; in xilinx_dma_probe()
3062 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); in xilinx_dma_probe()
3064 return -ENOMEM; in xilinx_dma_probe()
3066 xdev->dev = &pdev->dev; in xilinx_dma_probe()
3071 if (match && match->data) { in xilinx_dma_probe()
3072 xdev->dma_config = match->data; in xilinx_dma_probe()
3073 clk_init = xdev->dma_config->clk_init; in xilinx_dma_probe()
3077 err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk, in xilinx_dma_probe()
3078 &xdev->rx_clk, &xdev->rxs_clk); in xilinx_dma_probe()
3083 xdev->regs = devm_platform_ioremap_resource(pdev, 0); in xilinx_dma_probe()
3084 if (IS_ERR(xdev->regs)) { in xilinx_dma_probe()
3085 err = PTR_ERR(xdev->regs); in xilinx_dma_probe()
3089 xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); in xilinx_dma_probe()
3090 xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2; in xilinx_dma_probe()
3092 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA || in xilinx_dma_probe()
3093 xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { in xilinx_dma_probe()
3094 if (!of_property_read_u32(node, "xlnx,sg-length-width", in xilinx_dma_probe()
3098 dev_warn(xdev->dev, in xilinx_dma_probe()
3099 "invalid xlnx,sg-length-width property value. Using default width\n"); in xilinx_dma_probe()
3102 dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n"); in xilinx_dma_probe()
3103 xdev->max_buffer_len = in xilinx_dma_probe()
3104 GENMASK(len_width - 1, 0); in xilinx_dma_probe()
3109 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_probe()
3110 xdev->has_axistream_connected = in xilinx_dma_probe()
3111 of_property_read_bool(node, "xlnx,axistream-connected"); in xilinx_dma_probe()
3114 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in xilinx_dma_probe()
3115 err = of_property_read_u32(node, "xlnx,num-fstores", in xilinx_dma_probe()
3118 dev_err(xdev->dev, in xilinx_dma_probe()
3119 "missing xlnx,num-fstores property\n"); in xilinx_dma_probe()
3123 err = of_property_read_u32(node, "xlnx,flush-fsync", in xilinx_dma_probe()
3124 &xdev->flush_on_fsync); in xilinx_dma_probe()
3126 dev_warn(xdev->dev, in xilinx_dma_probe()
3127 "missing xlnx,flush-fsync property\n"); in xilinx_dma_probe()
3132 dev_warn(xdev->dev, "missing xlnx,addrwidth property\n"); in xilinx_dma_probe()
3135 xdev->ext_addr = true; in xilinx_dma_probe()
3137 xdev->ext_addr = false; in xilinx_dma_probe()
3140 if (xdev->has_axistream_connected) in xilinx_dma_probe()
3141 xdev->common.desc_metadata_modes = DESC_METADATA_ENGINE; in xilinx_dma_probe()
3144 err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width)); in xilinx_dma_probe()
3146 dev_err(xdev->dev, "DMA mask error %d\n", err); in xilinx_dma_probe()
3151 xdev->common.dev = &pdev->dev; in xilinx_dma_probe()
3153 INIT_LIST_HEAD(&xdev->common.channels); in xilinx_dma_probe()
3154 if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) { in xilinx_dma_probe()
3155 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask); in xilinx_dma_probe()
3156 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); in xilinx_dma_probe()
3159 xdev->common.device_alloc_chan_resources = in xilinx_dma_probe()
3161 xdev->common.device_free_chan_resources = in xilinx_dma_probe()
3163 xdev->common.device_terminate_all = xilinx_dma_terminate_all; in xilinx_dma_probe()
3164 xdev->common.device_synchronize = xilinx_dma_synchronize; in xilinx_dma_probe()
3165 xdev->common.device_tx_status = xilinx_dma_tx_status; in xilinx_dma_probe()
3166 xdev->common.device_issue_pending = xilinx_dma_issue_pending; in xilinx_dma_probe()
3167 xdev->common.device_config = xilinx_dma_device_config; in xilinx_dma_probe()
3168 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_probe()
3169 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask); in xilinx_dma_probe()
3170 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg; in xilinx_dma_probe()
3171 xdev->common.device_prep_dma_cyclic = in xilinx_dma_probe()
3173 /* Residue calculation is supported by only AXI DMA and CDMA */ in xilinx_dma_probe()
3174 xdev->common.residue_granularity = in xilinx_dma_probe()
3176 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_probe()
3177 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask); in xilinx_dma_probe()
3178 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy; in xilinx_dma_probe()
3179 /* Residue calculation is supported by only AXI DMA and CDMA */ in xilinx_dma_probe()
3180 xdev->common.residue_granularity = in xilinx_dma_probe()
3182 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { in xilinx_dma_probe()
3183 xdev->common.device_prep_slave_sg = xilinx_mcdma_prep_slave_sg; in xilinx_dma_probe()
3185 xdev->common.device_prep_interleaved_dma = in xilinx_dma_probe()
3200 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in xilinx_dma_probe()
3201 for (i = 0; i < xdev->dma_config->max_channels; i++) in xilinx_dma_probe()
3202 if (xdev->chan[i]) in xilinx_dma_probe()
3203 xdev->chan[i]->num_frms = num_frames; in xilinx_dma_probe()
3207 err = dma_async_device_register(&xdev->common); in xilinx_dma_probe()
3209 dev_err(xdev->dev, "failed to register the dma device\n"); in xilinx_dma_probe()
3216 dev_err(&pdev->dev, "Unable to register DMA to DT\n"); in xilinx_dma_probe()
3217 dma_async_device_unregister(&xdev->common); in xilinx_dma_probe()
3221 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) in xilinx_dma_probe()
3222 dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n"); in xilinx_dma_probe()
3223 else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) in xilinx_dma_probe()
3224 dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n"); in xilinx_dma_probe()
3225 else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) in xilinx_dma_probe()
3226 dev_info(&pdev->dev, "Xilinx AXI MCDMA Engine Driver Probed!!\n"); in xilinx_dma_probe()
3228 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n"); in xilinx_dma_probe()
3233 for (i = 0; i < xdev->dma_config->max_channels; i++) in xilinx_dma_probe()
3234 if (xdev->chan[i]) in xilinx_dma_probe()
3235 xilinx_dma_chan_remove(xdev->chan[i]); in xilinx_dma_probe()
3243 * xilinx_dma_remove - Driver remove function
3253 of_dma_controller_free(pdev->dev.of_node); in xilinx_dma_remove()
3255 dma_async_device_unregister(&xdev->common); in xilinx_dma_remove()
3257 for (i = 0; i < xdev->dma_config->max_channels; i++) in xilinx_dma_remove()
3258 if (xdev->chan[i]) in xilinx_dma_remove()
3259 xilinx_dma_chan_remove(xdev->chan[i]); in xilinx_dma_remove()
3268 .name = "xilinx-vdma",