13724e186SJoakim Zhang===================================================== 23724e186SJoakim ZhangFreescale i.MX8 DDR Performance Monitoring Unit (PMU) 33724e186SJoakim Zhang===================================================== 43724e186SJoakim Zhang 53724e186SJoakim ZhangThere are no performance counters inside the DRAM controller, so performance 63724e186SJoakim Zhangsignals are brought out to the edge of the controller where a set of 4 x 32 bit 7*751d5b27SAndrew Klychkovcounters is implemented. This is controlled by the CSV modes programmed in counter 83724e186SJoakim Zhangcontrol register which causes a large number of PERF signals to be generated. 93724e186SJoakim Zhang 103724e186SJoakim ZhangSelection of the value for each counter is done via the config registers. There 113724e186SJoakim Zhangis one register for each counter. Counter 0 is special in that it always counts 123724e186SJoakim Zhang“time” and when expired causes a lock on itself and the other counters and an 133724e186SJoakim Zhanginterrupt is raised. If any other counter overflows, it continues counting, and 143724e186SJoakim Zhangno interrupt is raised. 153724e186SJoakim Zhang 163724e186SJoakim ZhangThe "format" directory describes format of the config (event ID) and config1 173724e186SJoakim Zhang(AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/ 183724e186SJoakim Zhangdevices/imx8_ddr0/format/. The "events" directory describes the events types 193724e186SJoakim Zhanghardware supported that can be used with perf tool, see /sys/bus/event_source/ 20ed0207a3SJoakim Zhangdevices/imx8_ddr0/events/. The "caps" directory describes filter features implemented 21ed0207a3SJoakim Zhangin DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/. 220522e130SAdam Zerella 230522e130SAdam Zerella .. code-block:: bash 240522e130SAdam Zerella 253724e186SJoakim Zhang perf stat -a -e imx8_ddr0/cycles/ cmd 263724e186SJoakim Zhang perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd 273724e186SJoakim Zhang 283724e186SJoakim ZhangAXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write) 293724e186SJoakim Zhangto count reading or writing matches filter setting. Filter setting is various 303724e186SJoakim Zhangfrom different DRAM controller implementations, which is distinguished by quirks 31ed0207a3SJoakim Zhangin the driver. You also can dump info from userspace, filter in "caps" directory 32ed0207a3SJoakim Zhangindicates whether PMU supports AXI ID filter or not; enhanced_filter indicates 33ed0207a3SJoakim Zhangwhether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and 34ed0207a3SJoakim Zhangvalue 1 for supported. 353724e186SJoakim Zhang 36ed0207a3SJoakim Zhang* With DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0). 373724e186SJoakim Zhang Filter is defined with two configuration parts: 383724e186SJoakim Zhang --AXI_ID defines AxID matching value. 393724e186SJoakim Zhang --AXI_MASKING defines which bits of AxID are meaningful for the matching. 400522e130SAdam Zerella 410522e130SAdam Zerella - 0: corresponding bit is masked. 420522e130SAdam Zerella - 1: corresponding bit is not masked, i.e. used to do the matching. 433724e186SJoakim Zhang 443724e186SJoakim Zhang AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter. 453724e186SJoakim Zhang When non-masked bits are matching corresponding AXI_ID bits then counter is 462b008dc6SMauro Carvalho Chehab incremented. Perf counter is incremented if:: 472b008dc6SMauro Carvalho Chehab 483724e186SJoakim Zhang AxID && AXI_MASKING == AXI_ID && AXI_MASKING 493724e186SJoakim Zhang 503724e186SJoakim Zhang This filter doesn't support filter different AXI ID for axid-read and axid-write 513724e186SJoakim Zhang event at the same time as this filter is shared between counters. 520522e130SAdam Zerella 530522e130SAdam Zerella .. code-block:: bash 540522e130SAdam Zerella 553724e186SJoakim Zhang perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd 563724e186SJoakim Zhang perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd 573724e186SJoakim Zhang 580522e130SAdam Zerella .. note:: 590522e130SAdam Zerella 600522e130SAdam Zerella axi_mask is inverted in userspace(i.e. set bits are bits to mask), and 613724e186SJoakim Zhang it will be reverted in driver automatically. so that the user can just specify 623724e186SJoakim Zhang axi_id to monitor a specific id, rather than having to specify axi_mask. 630522e130SAdam Zerella 640522e130SAdam Zerella .. code-block:: bash 650522e130SAdam Zerella 663724e186SJoakim Zhang perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12 6776d835fcSJoakim Zhang 68ed0207a3SJoakim Zhang* With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1). 6976d835fcSJoakim Zhang This is an extension to the DDR_CAP_AXI_ID_FILTER quirk which permits 7076d835fcSJoakim Zhang counting the number of bytes (as opposed to the number of bursts) from DDR 7176d835fcSJoakim Zhang read and write transactions concurrently with another set of data counters. 72