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/openbmc/linux/drivers/memory/tegra/
H A Dtegra186.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved.
14 #include <soc/tegra/mc.h>
17 #include <dt-bindings/memory/tegra186-mc.h>
20 #include "mc.h"
26 static int tegra186_mc_probe(struct tegra_mc *mc) in tegra186_mc_probe() argument
28 struct platform_device *pdev = to_platform_device(mc->dev); in tegra186_mc_probe()
33 mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast"); in tegra186_mc_probe()
34 if (IS_ERR(mc->bcast_ch_regs)) { in tegra186_mc_probe()
35 if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) { in tegra186_mc_probe()
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H A Dtegra234.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2022-2023, NVIDIA CORPORATION. All rights reserved.
6 #include <soc/tegra/mc.h>
8 #include <dt-bindings/memory/tegra234-mc.h>
10 #include <linux/tegra-icc.h>
13 #include "mc.h"
16 * MC Client entries are sorted in the increasing order of the
25 .sid = TEGRA234_SID_HDA,
27 .sid = {
37 .sid = TEGRA234_SID_NVENC,
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H A Dtegra194.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved.
6 #include <soc/tegra/mc.h>
8 #include <dt-bindings/memory/tegra194-mc.h>
10 #include "mc.h"
16 .sid = TEGRA194_SID_PASSTHROUGH,
18 .sid = {
26 .sid = TEGRA194_SID_MIU,
28 .sid = {
36 .sid = TEGRA194_SID_MIU,
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra186-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
15 into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
16 handles memory requests for 40-bit virtual addresses from internal clients
27 pattern: "^memory-controller@[0-9a-f]+$"
31 - enum:
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/openbmc/qemu/hw/arm/
H A Dorangepi.c22 #include "exec/address-spaces.h"
24 #include "qemu/error-report.h"
26 #include "hw/qdev-properties.h"
27 #include "hw/arm/allwinner-h3.h"
41 if (machine->firmware) { in orangepi_init()
47 if (machine->ram_size != 1 * GiB) { in orangepi_init()
57 object_property_set_int(OBJECT(h3), "clk0-freq", 32768, &error_abort); in orangepi_init()
58 object_property_set_int(OBJECT(h3), "clk1-freq", 24 * 1000 * 1000, in orangepi_init()
61 /* Setup SID properties. Currently using a default fixed SID identifier. */ in orangepi_init()
62 if (qemu_uuid_is_null(&h3->sid.identifier)) { in orangepi_init()
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/openbmc/linux/include/soc/tegra/
H A Dmc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #include <linux/interconnect-provider.h>
14 #include <linux/reset-controller.h>
16 #include <linux/tegra-icc.h>
40 unsigned int sid; member
64 } sid; member
104 struct tegra_mc *mc);
109 struct tegra_mc *mc) in tegra_smmu_probe() argument
120 struct gart_device *tegra_gart_probe(struct device *dev, struct tegra_mc *mc);
125 tegra_gart_probe(struct device *dev, struct tegra_mc *mc) in tegra_gart_probe() argument
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/openbmc/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-nvidia.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 NVIDIA CORPORATION. All rights reserved.
10 #include <soc/tegra/mc.h>
12 #include "arm-smmu.h"
15 * Tegra194 has three ARM MMU-500 Instances.
18 * non-isochronous HW devices.
22 * driver to ensure that the right SID override is programmed for any given
23 * memory client. This is necessary to allow for use-case such as seamlessly
29 * driver for SID override programming after devices have been attached to an
38 struct tegra_mc *mc; member
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H A Darm-smmu.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * - SMMUv1 and v2 implementations
11 * - Stream-matching and stream-indexing
12 * - v7/v8 long-descriptor format
13 * - Non-secure access to the SMMU
14 * - Context fault reporting
15 * - Extended Stream ID (16 bit)
18 #define pr_fmt(fmt) "arm-smmu: " fmt
24 #include <linux/dma-mapping.h>
38 #include <linux/fsl/mc.h>
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/openbmc/linux/drivers/dma/
H A Dtegra186-gpc-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
10 #include <linux/dma-mapping.h>
21 #include <dt-bindings/memory/tegra186-mc.h>
22 #include "virt-dma.h"
87 /* MC sequence register */
118 (GENMASK((fls(bs) - 2), 0) << TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT)
158 * on-flight burst and update DMA status register.
203 * sub-transfer as per requester details and hw support. This sub transfer
264 writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg); in tdc_write()
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/openbmc/linux/Documentation/arch/ia64/
H A Derr_inject.rst2 IPF Machine Check (MC) error inject tool
5 IPF Machine Check (MC) error inject tool is used to inject MC
6 errors from Linux. The tool is a test bed for IPF MC work flow including
7 hardware correctable error handling, OS recoverable error handling, MC
17 The tool can be used to test Intel IPF machine MC handling capabilities.
18 It's especially useful for people who can not access hardware MC injection
50 #corrected, data cache, hier-2, physical addr(assigned by tool code).
55 #corrected, data cache, hier-2, physical addr(assigned by tool code).
60 #recoverable, DTR0, hier-2.
111 #define ERR_DATA_BUFFER_SIZE 3 // Three 8-byte.
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/openbmc/qemu/ui/
H A Dspice-display.c19 #include "ui/qemu-spice.h"
20 #include "qemu/error-report.h"
23 #include "qemu/main-loop.h"
29 #include "ui/spice-display.h"
35 return r->top == r->bottom || r->left == r->right; in qemu_spice_rect_is_empty()
49 dest->top = MIN(dest->top, r->top); in qemu_spice_rect_union()
50 dest->left = MIN(dest->left, r->left); in qemu_spice_rect_union()
51 dest->bottom = MAX(dest->bottom, r->bottom); in qemu_spice_rect_union()
52 dest->right = MAX(dest->right, r->right); in qemu_spice_rect_union()
60 cookie->type = type; in qxl_cookie_new()
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/openbmc/linux/drivers/infiniband/core/
H A Dcma.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
4 * Copyright (c) 2002-2005, Network Appliance, Inc. All rights reserved.
5 * Copyright (c) 1999-2019, Mellanox Technologies, Inc. All rights reserved.
6 * Copyright (c) 2005-2006 Intel Corporation. All rights reserved.
87 if (rdma_ib_or_roce(id->device, id->port_num)) in rdma_reject_msg()
90 if (rdma_protocol_iwarp(id->device, id->port_num)) in rdma_reject_msg()
99 * rdma_is_consumer_reject - return true if the consumer rejected the connect
106 if (rdma_ib_or_roce(id->device, id->port_num)) in rdma_is_consumer_reject()
109 if (rdma_protocol_iwarp(id->device, id->port_num)) in rdma_is_consumer_reject()
110 return reason == -ECONNREFUSED; in rdma_is_consumer_reject()
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/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
[all …]
H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
[all …]
H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/dma/sun4i-a10.h>
49 #include <dt-bindings/reset/sun5i-ccu.h>
52 interrupt-parent = <&intc>;
55 #address-cells = <1>;
56 #size-cells = <0>;
60 compatible = "arm,cortex-a8";
[all …]
H A Dsun50i-a64.dtsi6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
46 #include <dt-bindings/clock/sun8i-de2.h>
47 #include <dt-bindings/clock/sun8i-r-ccu.h>
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/reset/sun50i-a64-ccu.h>
50 #include <dt-bindings/reset/sun8i-de2.h>
51 #include <dt-bindings/reset/sun8i-r-ccu.h>
54 interrupt-parent = <&gic>;
55 #address-cells = <1>;
[all …]
H A Dsun8i-a83t.dtsi6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51 #include <dt-bindings/reset/sun8i-de2.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
55 interrupt-parent = <&gic>;
56 #address-cells = <1>;
[all …]
H A Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <1>;
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
[all …]
/openbmc/linux/arch/ia64/include/asm/
H A Dpal.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
9 * chapter 11 IA-64 Processor Abstraction Layer
11 * Copyright (C) 1998-2001 Hewlett-Packard Co
12 * David Mosberger-Tang <davidm@hpl.hp.com>
21 * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
30 * Note that some of these calls use a static-register only calling
66 #define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */
83 #define PAL_TEST_PROC 258 /* perform late processor self-test */
87 #define PAL_GET_PSTATE 262 /* get the current P-state */
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dgk104.c32 #include <subdev/mc.h>
42 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in gk104_chan_stop()
44 nvkm_mask(device, 0x800004 + (chan->id * 8), 0x00000800, 0x00000800); in gk104_chan_stop()
50 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in gk104_chan_start()
52 nvkm_mask(device, 0x800004 + (chan->id * 8), 0x00000400, 0x00000400); in gk104_chan_start()
58 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in gk104_chan_unbind()
60 nvkm_wr32(device, 0x800000 + (chan->id * 8), 0x00000000); in gk104_chan_unbind()
66 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in gk104_chan_bind_inst()
68 nvkm_wr32(device, 0x800000 + (chan->id * 8), 0x80000000 | chan->inst->addr >> 12); in gk104_chan_bind_inst()
74 struct nvkm_runl *runl = chan->cgrp->runl; in gk104_chan_bind()
[all …]
/openbmc/linux/arch/riscv/boot/dts/allwinner/
H A Dsunxi-d1s-t113.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
4 #include <dt-bindings/clock/sun6i-rtc.h>
5 #include <dt-bindings/clock/sun8i-de2.h>
6 #include <dt-bindings/clock/sun8i-tcon-top.h>
7 #include <dt-bindings/clock/sun20i-d1-ccu.h>
8 #include <dt-bindings/clock/sun20i-d1-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/reset/sun8i-de2.h>
11 #include <dt-bindings/reset/sun20i-d1-ccu.h>
[all …]
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h6.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-tcon-top.h>
10 #include <dt-bindings/reset/sun50i-h6-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dsi.c43 #include "sid.h"
1230 switch (rdev->family) { in si_init_golden_registers()
1298 * si_get_allowed_info_register - fetch the register for the info ioctl
1304 * Returns 0 for success or -EINVAL for an invalid register
1323 return -EINVAL; in si_get_allowed_info_register()
1331 * si_get_xclk - get the xclk
1340 u32 reference_clock = rdev->clock.spll.reference_freq; in si_get_xclk()
1580 if (!rdev->mc_fw) in si_mc_load_microcode()
1581 return -EINVAL; in si_mc_load_microcode()
1583 if (rdev->new_fw) { in si_mc_load_microcode()
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