Lines Matching +full:mc +full:- +full:sid
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2022-2023, NVIDIA CORPORATION. All rights reserved.
6 #include <soc/tegra/mc.h>
8 #include <dt-bindings/memory/tegra234-mc.h>
10 #include <linux/tegra-icc.h>
13 #include "mc.h"
16 * MC Client entries are sorted in the increasing order of the
25 .sid = TEGRA234_SID_HDA,
27 .sid = {
37 .sid = TEGRA234_SID_NVENC,
39 .sid = {
49 .sid = TEGRA234_SID_PCIE6,
51 .sid = {
61 .sid = TEGRA234_SID_PCIE6,
63 .sid = {
73 .sid = TEGRA234_SID_PCIE7,
75 .sid = {
85 .sid = TEGRA234_SID_NVENC,
87 .sid = {
95 .sid = TEGRA234_SID_NVDLA0,
97 .sid = {
105 .sid = TEGRA234_SID_NVDLA0,
107 .sid = {
115 .sid = TEGRA234_SID_NVDLA0,
117 .sid = {
125 .sid = TEGRA234_SID_NVDLA1,
127 .sid = {
137 .sid = TEGRA234_SID_PCIE7,
139 .sid = {
149 .sid = TEGRA234_SID_PCIE8,
151 .sid = {
161 .sid = TEGRA234_SID_HDA,
163 .sid = {
173 .sid = TEGRA234_SID_PCIE8,
175 .sid = {
185 .sid = TEGRA234_SID_PCIE9,
187 .sid = {
197 .sid = TEGRA234_SID_PCIE6,
199 .sid = {
209 .sid = TEGRA234_SID_PCIE9,
211 .sid = {
221 .sid = TEGRA234_SID_PCIE10,
223 .sid = {
233 .sid = TEGRA234_SID_PCIE10,
235 .sid = {
245 .sid = TEGRA234_SID_PCIE10,
247 .sid = {
257 .sid = TEGRA234_SID_PCIE7,
259 .sid = {
269 .sid = TEGRA234_SID_MGBE,
271 .sid = {
281 .sid = TEGRA234_SID_MGBE_VF1,
283 .sid = {
293 .sid = TEGRA234_SID_MGBE_VF2,
295 .sid = {
305 .sid = TEGRA234_SID_MGBE_VF3,
307 .sid = {
317 .sid = TEGRA234_SID_MGBE,
319 .sid = {
329 .sid = TEGRA234_SID_MGBE_VF1,
331 .sid = {
341 .sid = TEGRA234_SID_MGBE_VF2,
343 .sid = {
353 .sid = TEGRA234_SID_SDMMC4,
355 .sid = {
365 .sid = TEGRA234_SID_MGBE_VF3,
367 .sid = {
377 .sid = TEGRA234_SID_SDMMC4,
379 .sid = {
389 .sid = TEGRA234_SID_VIC,
391 .sid = {
401 .sid = TEGRA234_SID_VIC,
403 .sid = {
411 .sid = TEGRA234_SID_NVDLA1,
413 .sid = {
421 .sid = TEGRA234_SID_NVDLA1,
423 .sid = {
433 .sid = TEGRA234_SID_ISO_VI2,
435 .sid = {
445 .sid = TEGRA234_SID_ISO_VI2FALC,
447 .sid = {
457 .sid = TEGRA234_SID_NVDEC,
459 .sid = {
469 .sid = TEGRA234_SID_NVDEC,
471 .sid = {
481 .sid = TEGRA234_SID_APE,
483 .sid = {
493 .sid = TEGRA234_SID_APE,
495 .sid = {
505 .sid = TEGRA234_SID_ISO_VI2FALC,
507 .sid = {
517 .sid = TEGRA234_SID_NVJPG,
519 .sid = {
529 .sid = TEGRA234_SID_NVJPG,
531 .sid = {
541 .sid = TEGRA234_SID_ISO_NVDISPLAY,
543 .sid = {
551 .sid = TEGRA234_SID_BPMP,
553 .sid = {
561 .sid = TEGRA234_SID_BPMP,
563 .sid = {
571 .sid = TEGRA234_SID_BPMP,
573 .sid = {
581 .sid = TEGRA234_SID_BPMP,
583 .sid = {
593 .sid = TEGRA234_SID_APE,
595 .sid = {
605 .sid = TEGRA234_SID_APE,
607 .sid = {
617 .sid = TEGRA234_SID_ISO_NVDISPLAY,
619 .sid = {
627 .sid = TEGRA234_SID_NVDLA0,
629 .sid = {
637 .sid = TEGRA234_SID_NVDLA0,
639 .sid = {
647 .sid = TEGRA234_SID_NVDLA0,
649 .sid = {
657 .sid = TEGRA234_SID_NVDLA0,
659 .sid = {
667 .sid = TEGRA234_SID_NVDLA1,
669 .sid = {
677 .sid = TEGRA234_SID_NVDLA1,
679 .sid = {
687 .sid = TEGRA234_SID_NVDLA1,
689 .sid = {
697 .sid = TEGRA234_SID_NVDLA1,
699 .sid = {
709 .sid = TEGRA234_SID_PCIE0,
711 .sid = {
721 .sid = TEGRA234_SID_PCIE0,
723 .sid = {
733 .sid = TEGRA234_SID_PCIE1,
735 .sid = {
745 .sid = TEGRA234_SID_PCIE1,
747 .sid = {
757 .sid = TEGRA234_SID_PCIE2,
759 .sid = {
769 .sid = TEGRA234_SID_PCIE2,
771 .sid = {
781 .sid = TEGRA234_SID_PCIE3,
783 .sid = {
793 .sid = TEGRA234_SID_PCIE3,
795 .sid = {
805 .sid = TEGRA234_SID_PCIE4,
807 .sid = {
817 .sid = TEGRA234_SID_PCIE4,
819 .sid = {
829 .sid = TEGRA234_SID_PCIE5,
831 .sid = {
841 .sid = TEGRA234_SID_PCIE5,
843 .sid = {
851 .sid = TEGRA234_SID_NVDLA0,
853 .sid = {
861 .sid = TEGRA234_SID_NVDLA1,
863 .sid = {
873 .sid = TEGRA234_SID_PCIE5,
875 .sid = {
885 .sid = TEGRA234_SID_NVJPG1,
887 .sid = {
897 .sid = TEGRA234_SID_NVJPG1,
899 .sid = {
933 * tegra234_mc_icc_set() - Pass MC client info to the BPMP-FW
934 * @src: ICC node for Memory Controller's (MC) Client
935 * @dst: ICC node for Memory Controller (MC)
937 * Passing the current request info from the MC to the BPMP-FW where
940 * icc_set_bw() makes set_bw calls for both MC and EMC providers in
947 struct tegra_mc *mc = icc_provider_to_tegra_mc(dst->provider); in tegra234_mc_icc_set() local
950 const struct tegra_mc_client *pclient = src->data; in tegra234_mc_icc_set()
956 * This can be used to pre-initialize and set bandwidth for all clients in tegra234_mc_icc_set()
958 * the pre-initialization already happened in Bootloader(MB2) and BPMP-FW. in tegra234_mc_icc_set()
960 if (src->id == dst->id) in tegra234_mc_icc_set()
963 if (!mc->bwmgr_mrq_supported) in tegra234_mc_icc_set()
966 if (!mc->bpmp) { in tegra234_mc_icc_set()
967 dev_err(mc->dev, "BPMP reference NULL\n"); in tegra234_mc_icc_set()
968 return -ENOENT; in tegra234_mc_icc_set()
971 if (pclient->type == TEGRA_ICC_NISO) in tegra234_mc_icc_set()
972 bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw; in tegra234_mc_icc_set()
974 bwmgr_req.bwmgr_calc_set_req.iso_bw = src->avg_bw; in tegra234_mc_icc_set()
976 bwmgr_req.bwmgr_calc_set_req.client_id = pclient->bpmp_id; in tegra234_mc_icc_set()
979 bwmgr_req.bwmgr_calc_set_req.mc_floor = src->peak_bw; in tegra234_mc_icc_set()
989 if (pclient->bpmp_id >= TEGRA_ICC_BPMP_CPU_CLUSTER0 && in tegra234_mc_icc_set()
990 pclient->bpmp_id <= TEGRA_ICC_BPMP_CPU_CLUSTER2) in tegra234_mc_icc_set()
993 ret = tegra_bpmp_transfer(mc->bpmp, &msg); in tegra234_mc_icc_set()
995 dev_err(mc->dev, "BPMP transfer failed: %d\n", ret); in tegra234_mc_icc_set()
1001 ret = -EINVAL; in tegra234_mc_icc_set()
1011 struct icc_provider *p = node->provider; in tegra234_mc_icc_aggregate()
1012 struct tegra_mc *mc = icc_provider_to_tegra_mc(p); in tegra234_mc_icc_aggregate() local
1014 if (!mc->bwmgr_mrq_supported) in tegra234_mc_icc_aggregate()
1017 if (node->id == TEGRA_ICC_MC_CPU_CLUSTER0 || in tegra234_mc_icc_aggregate()
1018 node->id == TEGRA_ICC_MC_CPU_CLUSTER1 || in tegra234_mc_icc_aggregate()
1019 node->id == TEGRA_ICC_MC_CPU_CLUSTER2) { in tegra234_mc_icc_aggregate()
1020 if (mc) in tegra234_mc_icc_aggregate()
1021 peak_bw = peak_bw * mc->num_channels; in tegra234_mc_icc_aggregate()