| /openbmc/qemu/include/hw/i2c/ |
| H A D | pmbus_device.h | 16 PMBUS_PAGE = 0x00, /* R/W byte */
17 PMBUS_OPERATION = 0x01, /* R/W byte */
18 PMBUS_ON_OFF_CONFIG = 0x02, /* R/W byte */
20 PMBUS_PHASE = 0x04, /* R/W byte */
23 PMBUS_WRITE_PROTECT = 0x10, /* R/W byte */
35 PMBUS_VOUT_MODE = 0x20, /* R/W byte */
36 PMBUS_VOUT_COMMAND = 0x21, /* R/W word */
37 PMBUS_VOUT_TRIM = 0x22, /* R/W word */
38 PMBUS_VOUT_CAL_OFFSET = 0x23, /* R/W word */
39 PMBUS_VOUT_MAX = 0x24, /* R/W word */
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| /openbmc/linux/drivers/comedi/drivers/ |
| H A D | ni_labpc_regs.h | 17 #define STAT1_GATA0 BIT(5)
19 #define CMD1_REG 0x00 /* W: Command 1 reg */
24 #define CMD2_REG 0x01 /* W: Command 2 reg */
30 #define CMD2_2SDAC1 BIT(5)
32 #define CMD3_REG 0x02 /* W: Command 3 reg */
38 #define CMD3_FIFOINTEN BIT(5)
39 #define ADC_START_CONVERT_REG 0x03 /* W: Start Convert reg */
40 #define DAC_LSB_REG(x) (0x04 + 2 * (x)) /* W: DAC0/1 LSB reg */
41 #define DAC_MSB_REG(x) (0x05 + 2 * (x)) /* W: DAC0/1 MSB reg */
42 #define ADC_FIFO_CLEAR_REG 0x08 /* W: A/D FIFO Clear reg */
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| /openbmc/u-boot/lib/libavb/ |
| H A D | avb_sha256.c | 42 { w[i] = SHA256_F4(w[i - 2]) + w[i - 7] + SHA256_F3(w[i - 15]) + w[i - 16]; }
47 w[j]; \
88 ctx->h[5] = sha256_h0[5]; in avb_sha256_init()
100 uint32_t w[64]; in SHA256_transform() local
115 PACK32(&sub_block[j << 2], &w[j]); in SHA256_transform()
127 t1 = wv[7] + SHA256_F2(wv[4]) + CH(wv[4], wv[5], wv[6]) + sha256_k[j] + in SHA256_transform()
128 w[j]; in SHA256_transform()
131 wv[6] = wv[5]; in SHA256_transform()
132 wv[5] = wv[4]; in SHA256_transform()
144 PACK32(&sub_block[0], &w[0]); in SHA256_transform()
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| H A D | avb_sha512.c | 36 *((str) + 5) = (uint8_t)((uint64_t)x >> 16); \
48 ((uint64_t) * ((str) + 5) << 16) | ((uint64_t) * ((str) + 4) << 24) | \
56 { w[i] = SHA512_F4(w[i - 2]) + w[i - 7] + SHA512_F3(w[i - 15]) + w[i - 16]; }
61 w[j]; \
114 ctx->h[5] = sha512_h0[5]; in avb_sha512_init()
131 uint64_t w[80]; in SHA512_transform() local
141 PACK64(&sub_block[0], &w[0]); in SHA512_transform()
142 PACK64(&sub_block[8], &w[1]); in SHA512_transform()
143 PACK64(&sub_block[16], &w[2]); in SHA512_transform()
144 PACK64(&sub_block[24], &w[3]); in SHA512_transform()
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| /openbmc/linux/drivers/scsi/ |
| H A D | nsp32.h | 37 MODEL_PCI_LOGITEC = 5,
81 #define IRQ_CONTROL 0x00 /* BASE+00, W, W */
82 #define IRQ_STATUS 0x00 /* BASE+00, W, R */
88 # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)
112 #define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
113 #define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
119 # define NO_TRANSFER_TO_HOST BIT(5)
130 #define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
132 #define TIMER_SET 0x06 /* BASE+06, W, R/W */
136 #define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
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| H A D | fdomain.h | 16 #define REG_SCSI_DATA 0 /* R/W: SCSI Data (with ACK) */
23 #define BSTAT_SEL BIT(5) /* Select */
26 #define REG_BCTL 1 /* W: SCSI Bus Control */
32 #define BCTL_CMD BIT(5) /* Command/Data */
41 #define ASTAT_FIFOEN BIT(5) /* FIFO enabled */
44 #define REG_ICTL 2 /* W: Interrupt Control */
47 #define ICTL_ARB BIT(5) /* Int. on Arbitration complete */
55 #define REG_MCTL 3 /* W: SCSI Data Mode Control */
58 #define MCTL_TARGET BIT(5) /* Enable target mode */
66 #define IRQ_RST BIT(5) /* SCSI Reset interrupt */
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| /openbmc/qemu/target/mips/tcg/ |
| H A D | msa_helper.c | 59 * | NLOC.W | Vector Leading Ones Count (word) |
63 * | NLZC.W | Vector Leading Zeros Count (word) |
67 * | PCNT.W | Vector Population Count (word) |
108 pwd->b[5] = msa_nloc_df(DF_BYTE, pws->b[5]); in helper_msa_nloc_b()
131 pwd->h[5] = msa_nloc_df(DF_HALF, pws->h[5]); in helper_msa_nloc_h()
141 pwd->w[0] = msa_nloc_df(DF_WORD, pws->w[0]); in helper_msa_nloc_w()
142 pwd->w[1] = msa_nloc_df(DF_WORD, pws->w[1]); in helper_msa_nloc_w()
143 pwd->w[2] = msa_nloc_df(DF_WORD, pws->w[2]); in helper_msa_nloc_w()
144 pwd->w[3] = msa_nloc_df(DF_WORD, pws->w[3]); in helper_msa_nloc_w()
166 pwd->b[5] = msa_nlzc_df(DF_BYTE, pws->b[5]); in helper_msa_nlzc_b()
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| /openbmc/u-boot/arch/nios2/lib/ |
| H A D | libgcc.c | 39 0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
58 DWunion w; in __ashldi3() local
62 w.s.low = 0; in __ashldi3()
63 w.s.high = (UWtype) uu.s.low << -bm; in __ashldi3()
69 w.s.low = (UWtype) uu.s.low << b; in __ashldi3()
70 w.s.high = ((UWtype) uu.s.high << b) | carries; in __ashldi3()
73 return w.ll; in __ashldi3()
84 DWunion w; in __ashrdi3() local
88 /* w.s.high = 1..1 or 0..0 */ in __ashrdi3()
89 w.s.high = uu.s.high >> (sizeof (Wtype) * BITS_PER_UNIT - 1); in __ashrdi3()
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| /openbmc/qemu/hw/display/ |
| H A D | exynos4210_fimd.c | 64 #define NUM_OF_WINDOWS 5
109 #define IS_PALETTIZED_MODE(w) (w->wincon & 0xC) argument
111 #define WIN_BPP_MODE(w) ((w->wincon >> 2) & 0xF) argument
112 #define WIN_BPP_MODE_WITH_ALPHA(w) \ argument
113 (WIN_BPP_MODE(w) == 0xD || WIN_BPP_MODE(w) == 0xE)
117 #define FIMD_WINDOW_PROTECTED(s, w) ((s) & (1 << (10 + (w)))) argument
284 void (*draw_line)(Exynos4210fimdWindow *w, uint8_t *src, uint8_t *dst,
286 uint32_t (*get_alpha)(Exynos4210fimdWindow *w, uint32_t pix_a);
327 Exynos4210fimdWindow window[5]; /* Window-specific registers */
393 DEF_PIXEL_TO_RGB_A1(pixel_a555_to_rgb, 5, 5, 5)
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| /openbmc/qemu/host/include/i386/host/ |
| H A D | bufferiszero.c.inc | 20 __m128i w = *(__m128i_u *)(buf + len - 16);
27 v |= e[-1]; w |= e[-2];
28 SSE_REASSOC_BARRIER(v, w);
29 v |= e[-3]; w |= e[-4];
30 SSE_REASSOC_BARRIER(v, w);
31 v |= e[-5]; w |= e[-6];
32 SSE_REASSOC_BARRIER(v, w);
33 v |= e[-7]; v |= w;
45 v = p[0]; w = p[1];
46 SSE_REASSOC_BARRIER(v, w);
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| /openbmc/linux/arch/powerpc/crypto/ |
| H A D | sha1-powerpc-asm.S | 26 #define RT(t) ((((t)+5)%6)+7)
33 /* We use registers 16 - 31 for the W values */
34 #define W(t) (((t)%16)+16) macro
37 LWZ(W(t),(t)*4,r4)
42 rotlwi RT(t),RA(t),5; \
46 add r14,r0,W(t); \
47 LWZ(W((t)+4),((t)+4)*4,r4); \
54 rotlwi RT(t),RA(t),5; \
58 xor r5,W((t)+4-3),W((t)+4-8); \
60 xor W((t)+4),W((t)+4-16),W((t)+4-14); \
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| H A D | sha1-spe-asm.S | 107 LOAD_DATA(w0, off) /* 1: W */ \
111 rotrwi rT0,a,27; /* 1: A' = A rotl 5 */ \
115 add e,e,w0; /* 1: E = E + W */ \
116 LOAD_DATA(w1, off+4) /* 2: W */ \
123 rotrwi rT0,e,27; /* 2: A' = A rotl 5 */ \
124 add d,d,w1; /* 2: E = E + W */ \
127 evmergelo w1,w1,w0; /* mix W[0]/W[1] */ \
132 evmergelohi rT0,w7,w6; /* W[-3] */ \
134 evxor w0,w0,rT0; /* W = W[-16] xor W[-3] */ \
136 evxor w0,w0,w4; /* W = W xor W[-8] */ \
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| /openbmc/linux/arch/loongarch/lib/ |
| H A D | memcpy.S | 53 .align 5
56 slli.d a2, a2, 5
60 .align 5
63 .align 5
68 .align 5
73 .align 5
80 .align 5
81 4: ld.w t0, a1, 0
82 st.w t0, a0, 0
85 .align 5
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| H A D | copy_user.S | 79 5: ld.d t3, a1, 24
137 .align 5
140 slli.d a3, a2, 5
144 .align 5
148 .align 5
154 .align 5
160 .align 5
168 .align 5
169 42: ld.w t0, a1, 0
170 43: st.w t0, a0, 0
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| /openbmc/linux/lib/crypto/ |
| H A D | sha256.c | 54 static inline void LOAD_OP(int I, u32 *W, const u8 *input) in LOAD_OP() argument
56 W[I] = get_unaligned_be32((__u32 *)input + I); in LOAD_OP()
59 static inline void BLEND_OP(int I, u32 *W) in BLEND_OP() argument
61 W[I] = s1(W[I-2]) + W[I-7] + s0(W[I-15]) + W[I-16]; in BLEND_OP()
66 t1 = h + e1(e) + Ch(e, f, g) + SHA256_K[i] + W[i]; \
72 static void sha256_transform(u32 *state, const u8 *input, u32 *W) in sha256_transform() argument
79 LOAD_OP(i + 0, W, input); in sha256_transform()
80 LOAD_OP(i + 1, W, input); in sha256_transform()
81 LOAD_OP(i + 2, W, input); in sha256_transform()
82 LOAD_OP(i + 3, W, input); in sha256_transform()
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| /openbmc/linux/Documentation/driver-api/media/drivers/ |
| H A D | tuners.rst | 38 5: With FM
69 MF: BG LL w/ Secam (Multi France)
75 MK3 series introduced in 2002 w/ PHILIPS_MK3_API
81 4[01][0136][269]F[HYNR]5
82 40x2: Tuner (5V/33V), TEMIC_API.
83 40x6: Tuner 5V
91 F[HYNR]5
95 FR5: w/ FM radio
101 - TPI8NSR11 : NTSC J/M (TPI8NSR01 w/FM) (P,210/497)
102 - TPI8PSB11 : PAL B/G (TPI8PSB01 w/FM) (P,170/450)
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| /openbmc/linux/arch/x86/crypto/ |
| H A D | sha512-ssse3-asm.S | 99 # W[t]+K[t] (stack frame)
126 add WK_2(idx), T1 # W[t] + K[t] from message scheduler
130 add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h
132 add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
139 ror $5, tmp0 # 39 # tmp = a ror 5
140 xor a_64, tmp0 # tmp = (a ror 5) ^ a
142 ror $6, tmp0 # 34 # tmp = ((a ror 5) ^ a) ror 6
143 xor a_64, tmp0 # tmp = (((a ror 5) ^ a) ror 6) ^ a
155 # Two rounds are computed based on the values for K[t-2]+W[t-2] and
156 # K[t-1]+W[t-1] which were previously stored at WK_2 by the message
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| H A D | sha512-avx-asm.S | 78 # W[t] + K[t] | W[t+1] + K[t+1]
101 # W[t]+K[t] (stack frame)
132 add WK_2(idx), T1 # W[t] + K[t] from message scheduler
136 add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h
138 add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
145 RORQ tmp0, 5 # 39 # tmp = a ror 5
146 xor a_64, tmp0 # tmp = (a ror 5) ^ a
148 RORQ tmp0, 6 # 34 # tmp = ((a ror 5) ^ a) ror 6
149 xor a_64, tmp0 # tmp = (((a ror 5) ^ a) ror 6) ^ a
160 # Two rounds are computed based on the values for K[t-2]+W[t-2] and
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| H A D | sha1_ssse3_asm.S | 62 /* we keep window of 64 w[i]+K pre-calculated values in a circular buffer */
250 * RR does two rounds of SHA-1 back to back with W[] pre-calc
251 * t1 = F(b, c, d); e += w(i)
252 * e += t1; b <<= 30; d += w(i+1);
254 * d += t1; a <<= 5;
257 * t1 <<= 5;
270 rol $5, \a
273 ror $7, \a # (a <<r 5) >>r 7) => a <<r 30)
278 rol $5, T1
312 .set W, W0 define
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| /openbmc/linux/drivers/input/gameport/ |
| H A D | fm801-gp.c | 31 unsigned short w; in fm801_gp_cooked_read() local
33 w = inw(gameport->io + 2); in fm801_gp_cooked_read()
34 *buttons = (~w >> 14) & 0x03; in fm801_gp_cooked_read()
35 axes[0] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
36 w = inw(gameport->io + 4); in fm801_gp_cooked_read()
37 axes[1] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
38 w = inw(gameport->io + 6); in fm801_gp_cooked_read()
39 *buttons |= ((~w >> 14) & 0x03) << 2; in fm801_gp_cooked_read()
40 axes[2] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
41 w = inw(gameport->io + 8); in fm801_gp_cooked_read()
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| /openbmc/linux/drivers/staging/ks7010/ |
| H A D | ks_hostif.h | 93 * @DOT11_RTS_THRESHOLD: RTS Threshold (R/W)
94 * @DOT11_FRAGMENTATION_THRESHOLD: Fragment Threshold (R/W)
95 * @DOT11_PRIVACY_INVOKED: WEP ON/OFF (W)
96 * @DOT11_WEP_DEFAULT_KEY_ID: WEP Index (W)
97 * @DOT11_WEP_DEFAULT_KEY_VALUE1: WEP Key#1(TKIP AES: PairwiseTemporalKey) (W)
98 * @DOT11_WEP_DEFAULT_KEY_VALUE2: WEP Key#2(TKIP AES: GroupKey1) (W)
99 * @DOT11_WEP_DEFAULT_KEY_VALUE3: WEP Key#3(TKIP AES: GroupKey2) (W)
100 * @DOT11_WEP_DEFAULT_KEY_VALUE4: WEP Key#4 (W)
105 * @LOCAL_AP_SEARCH_INTERVAL: AP search interval (R/W)
106 * @LOCAL_CURRENTADDRESS: MAC Address change (W)
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| /openbmc/linux/arch/mips/kernel/ |
| H A D | r4k-bugs64.c | 3 * Copyright (C) 2003, 2004, 2007 Maciej W. Rozycki
43 void mult_sh_align_mod(long *v1, long *v2, long *w, in mult_sh_align_mod() argument
72 : "0" (5), "1" (8), "2" (5)); in mult_sh_align_mod()
86 "dsll32 %0, %4, %5\n\t" in mult_sh_align_mod()
88 "dsll32 %1, %4, %5\n\t" in mult_sh_align_mod()
115 *w = lw; in mult_sh_align_mod()
120 long v1[8], v2[8], w[8]; in check_mult_sh() local
134 mult_sh_align_mod(&v1[0], &v2[0], &w[0], 32, 0); in check_mult_sh()
135 mult_sh_align_mod(&v1[1], &v2[1], &w[1], 32, 1); in check_mult_sh()
136 mult_sh_align_mod(&v1[2], &v2[2], &w[2], 32, 2); in check_mult_sh()
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| /openbmc/linux/drivers/net/fddi/skfp/h/ |
| H A D | supern_2.h | 55 #define FS_SFRMTY1 (1<<5) /* frame-type bit (impementor) */
67 #define FRM_LLCS (5)
147 #define RD_FRM_LLCS (unsigned long)(5<<20)
235 * FORMAC+ read/write (r/w) registers
243 #define FM_IMSK1U 0x04 /* r/w upper 16-bit of IMSK 1 */
244 #define FM_IMSK1L 0x05 /* r/w lower 16-bit of IMSK 1 */
245 #define FM_IMSK2U 0x06 /* r/w upper 16-bit of IMSK 2 */
246 #define FM_IMSK2L 0x07 /* r/w lower 16-bit of IMSK 2 */
247 #define FM_SAID 0x08 /* r/w short addr.-individual */
248 #define FM_LAIM 0x09 /* r/w long addr.-ind. (MSW of LAID) */
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| /openbmc/linux/drivers/net/wireless/intersil/hostap/ |
| H A D | hostap_common.h | 27 #define HFA384X_RID_CNFWDSADDRESS1 0xFC11 /* AP f/w only */
28 #define HFA384X_RID_CNFWDSADDRESS2 0xFC12 /* AP f/w only */
29 #define HFA384X_RID_CNFWDSADDRESS3 0xFC13 /* AP f/w only */
30 #define HFA384X_RID_CNFWDSADDRESS4 0xFC14 /* AP f/w only */
31 #define HFA384X_RID_CNFWDSADDRESS5 0xFC15 /* AP f/w only */
32 #define HFA384X_RID_CNFWDSADDRESS6 0xFC16 /* AP f/w only */
33 #define HFA384X_RID_CNFMULTICASTPMBUFFERING 0xFC17 /* AP f/w only */
44 #define HFA384X_RID_CNFMAXASSOCSTA 0xFC2B /* AP f/w only */
47 #define HFA384X_RID_CNFHOSTAUTHENTICATION 0xFC2E /* AP f/w only */
52 #define HFA384X_RID_CNFAPPCFINFO 0xFC34 /* AP f/w only */
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| /openbmc/linux/drivers/net/ethernet/marvell/ |
| H A D | skge.h | 141 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
156 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
199 IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
225 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
242 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
306 GP_IO_5 = 1<<5, /* IO_5 pin */
397 PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
421 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
430 * Bank 4 - 5
520 SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
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