Lines Matching +full:5 +full:w
141 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
156 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
199 IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
225 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
242 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
306 GP_IO_5 = 1<<5, /* IO_5 pin */
397 PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
421 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
430 * Bank 4 - 5
520 SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
572 MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
604 MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
616 MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
656 LED_BLK_ON = 1<<5, /* Link LED Blinking On */
680 TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
724 CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
768 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
909 XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
930 PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
931 PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
934 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
937 PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
947 PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
951 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
954 PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
957 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
960 PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
962 PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
963 PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
964 PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
966 PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
969 PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
976 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
980 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
983 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
986 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
989 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
991 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
993 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
994 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
995 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
997 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
998 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
999 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1000 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1002 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1003 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1006 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1007 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1008 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1010 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1036 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1079 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1095 PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
1107 /***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/
1117 PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */
1131 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1162 /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
1174 PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
1192 PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */
1200 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1210 /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
1214 /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
1218 /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
1227 PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */
1242 PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */
1252 /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1263 PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */
1301 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1310 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1321 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1331 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1339 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1385 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1412 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1425 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1451 /* 100=5x; 101=6x; 110=7x; 111=8x */
1458 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1466 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1488 PULS_340MS = 5, /* 340 ms to 670 ms */
1502 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1508 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1519 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1522 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1528 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1564 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1595 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1603 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1620 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1621 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1622 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1623 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1624 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1625 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1627 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1628 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1629 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1630 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1631 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1632 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1635 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1636 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1637 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1638 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1646 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1647 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1648 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1651 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1652 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1653 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1723 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1730 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1741 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1752 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1763 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1771 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1787 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1802 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1806 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1814 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1816 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1832 GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
1861 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1879 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1894 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1956 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
1982 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
2004 XM_MMU_CMD = 0x0000, /* 16 bit r/w MMU Command Register */
2005 XM_POFF = 0x0008, /* 32 bit r/w Packet Offset Register */
2006 XM_BURST = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
2007 XM_1L_VLAN_TAG = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
2008 XM_2L_VLAN_TAG = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
2009 XM_TX_CMD = 0x0020, /* 16 bit r/w Transmit Command Register */
2010 XM_TX_RT_LIM = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
2011 XM_TX_STIME = 0x0028, /* 16 bit r/w Transmit Slottime Register */
2012 XM_TX_IPG = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
2013 XM_RX_CMD = 0x0030, /* 16 bit r/w Receive Command Register */
2014 XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */
2015 XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */
2016 XM_GP_PORT = 0x0040, /* 32 bit r/w General Purpose Port Register */
2017 XM_IMSK = 0x0044, /* 16 bit r/w Interrupt Mask Register */
2019 XM_HW_CFG = 0x004c, /* 16 bit r/w Hardware Config Register */
2020 XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
2021 XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
2022 XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */
2023 XM_HT_THR = 0x0066, /* 16 bit r/w Host Request Threshold */
2024 XM_PAUSE_DA = 0x0068, /* NA reg r/w Pause Destination Address */
2025 XM_CTL_PARA = 0x0070, /* 32 bit r/w Control Parameter Register */
2026 XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
2027 XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
2030 XM_EXM_START = 0x0080, /* r/w Start Address of the EXM Regs */
2035 XM_SRC_CHK = 0x0100, /* NA reg r/w Source Check Address Register */
2036 XM_SA = 0x0108, /* NA reg r/w Station Address Register */
2037 XM_HSM = 0x0110, /* 64 bit r/w Hash Match Address Registers */
2038 XM_RX_LO_WM = 0x0118, /* 16 bit r/w Receive Low Water Mark */
2039 XM_RX_HI_WM = 0x011a, /* 16 bit r/w Receive High Water Mark */
2040 XM_RX_THR = 0x011c, /* 32 bit r/w Receive Request Threshold */
2042 XM_MODE = 0x0124, /* 32 bit r/w Mode Register */
2046 XM_STAT_CMD = 0x0200, /* 16 bit r/w Statistics Command Register */
2049 XM_RX_EV_MSK = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
2050 XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
2108 /* XM_MMU_CMD 16 bit r/w MMU Command Register */
2116 XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */
2125 /* XM_TX_CMD 16 bit r/w Transmit Command Register */
2128 XM_TX_ENC_BYP = 1<<5, /* Bit 5: Set Encoder in Bypass Mode */
2136 /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
2140 /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
2144 /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
2148 /* XM_RX_CMD 16 bit r/w Receive Command Register */
2155 XM_RX_TP_MD = 1<<5, /* Bit 5: Enable transparent Mode */
2164 /* XM_GP_PORT 32 bit r/w General Purpose Port Register */
2167 XM_GP_FRC_INT = 1<<5, /* Bit 5: (sc) Force Interrupt */
2174 /* XM_IMSK 16 bit r/w Interrupt Mask Register */
2186 XM_IS_RXC_OV = 1<<5, /* Bit 5: Rx Counter Event Overflow */
2196 /* XM_HW_CFG 16 bit r/w Hardware Config Register */
2204 /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
2205 /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
2208 /* XM_TX_THR 16 bit r/w Tx Request Threshold */
2209 /* XM_HT_THR 16 bit r/w Host Request Threshold */
2210 /* XM_RX_THR 16 bit r/w Rx Request Threshold */
2225 XM_ST_UC = 1<<5, /* Bit 5: Unicast packet */
2233 /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
2234 /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
2240 #define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */
2243 /* XM_MODE 32 bit r/w Mode Register */
2270 XM_MD_DIS_MC = 1<<5, /* Bit 5: Disable Rx Multicast */
2282 /* XM_STAT_CMD 16 bit r/w Statistics Command Register */
2284 XM_SC_SNP_RXC = 1<<5, /* Bit 5: (sc) Snap Rx Counters */
2294 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
2320 XMR_UC_OK_OV = 1<<5, /* Bit 5: Rx Unicast Frame CntOv*/
2331 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
2353 XMT_UC_OK_OV = 1<<5, /* Bit 5: Tx Unicast Cnt Ov */
2540 xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8)); in xm_outhash()
2549 xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8)); in xm_outaddr()
2576 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8)); in gma_set_addr()