Lines Matching +full:5 +full:w
16 #define REG_SCSI_DATA 0 /* R/W: SCSI Data (with ACK) */
23 #define BSTAT_SEL BIT(5) /* Select */
26 #define REG_BCTL 1 /* W: SCSI Bus Control */
32 #define BCTL_CMD BIT(5) /* Command/Data */
41 #define ASTAT_FIFOEN BIT(5) /* FIFO enabled */
44 #define REG_ICTL 2 /* W: Interrupt Control */
47 #define ICTL_ARB BIT(5) /* Int. on Arbitration complete */
55 #define REG_MCTL 3 /* W: SCSI Data Mode Control */
58 #define MCTL_TARGET BIT(5) /* Enable target mode */
66 #define IRQ_RST BIT(5) /* SCSI Reset interrupt */
69 #define REG_ACTL 4 /* W: Adapter Control 1 */
75 #define ACTL_CLRFIRQ BIT(5) /* Clear Forced interrupt */
78 #define REG_ID_LSB 5 /* R: ID Code (LSB) */
79 #define REG_ACTL2 5 /* Adapter Control 2 - (@) */
83 #define REG_LOOPBACK 7 /* R/W: Loopback */
84 #define REG_SCSI_DATA_NOACK 8 /* R/W: SCSI Data (no ACK) */
96 #define REG_CFG2 11 /* R/W: Configuration Register 2 (@) */
102 #define REG_FIFO 12 /* R/W: FIFO */