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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sdm660-venus.yaml113 reg = <0x0cc00000 0xff000>;
119 interconnects = <&gnoc 0 &mnoc 13>,
123 iommus = <&mmss_smmu 0x400>,
124 <&mmss_smmu 0x401>,
125 <&mmss_smmu 0x40a>,
126 <&mmss_smmu 0x407>,
127 <&mmss_smmu 0x40e>,
128 <&mmss_smmu 0x40f>,
129 <&mmss_smmu 0x408>,
130 <&mmss_smmu 0x409>,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,qcm2290-mdss.yaml45 "^display-controller@[0-9a-f]+$":
51 "^dsi@[0-9a-f]+$":
57 "^phy@[0-9a-f]+$":
81 reg = <0x05e00000 0x1000>;
96 iommus = <&apps_smmu 0x420 0x2>,
97 <&apps_smmu 0x421 0x0>;
102 reg = <0x05e01000 0x8f000>,
103 <0x05eb0000 0x2008>;
117 interrupts = <0>;
121 #size-cells = <0>;
[all …]
H A Dqcom,sm6115-mdss.yaml33 "^display-controller@[0-9a-f]+$":
39 "^dsi@[0-9a-f]+$":
51 "^phy@[0-9a-f]+$":
74 reg = <0x05e00000 0x1000>;
85 iommus = <&apps_smmu 0x420 0x2>,
86 <&apps_smmu 0x421 0x0>;
91 reg = <0x05e01000 0x8f000>,
92 <0x05eb0000 0x2008>;
107 interrupts = <0>;
111 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dau8522_priv.h27 #define AU8522_ANALOG_MODE 0
88 #define AU8522_INPUT_CONTROL_REG081H 0x081
89 #define AU8522_PGA_CONTROL_REG082H 0x082
90 #define AU8522_CLAMPING_CONTROL_REG083H 0x083
92 #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H 0x0A3
93 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H 0x0A4
94 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H 0x0A5
95 #define AU8522_AGC_CONTROL_RANGE_REG0A6H 0x0A6
96 #define AU8522_SYSTEM_GAIN_CONTROL_REG0A7H 0x0A7
97 #define AU8522_TUNER_AGC_RF_STOP_REG0A8H 0x0A8
[all …]
/openbmc/linux/drivers/perf/
H A Dqcom_l2_pmu.c31 #define L2PMCR_NUM_EV_MASK 0x1F
33 #define L2PMCR 0x400
34 #define L2PMCNTENCLR 0x403
35 #define L2PMCNTENSET 0x404
36 #define L2PMINTENCLR 0x405
37 #define L2PMINTENSET 0x406
38 #define L2PMOVSCLR 0x407
39 #define L2PMOVSSET 0x408
40 #define L2PMCCNTCR 0x409
41 #define L2PMCCNTR 0x40A
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-core.h32 CX18_AV_SVIDEO_LUMA1 = 0x10,
33 CX18_AV_SVIDEO_LUMA2 = 0x20,
34 CX18_AV_SVIDEO_LUMA3 = 0x30,
35 CX18_AV_SVIDEO_LUMA4 = 0x40,
36 CX18_AV_SVIDEO_LUMA5 = 0x50,
37 CX18_AV_SVIDEO_LUMA6 = 0x60,
38 CX18_AV_SVIDEO_LUMA7 = 0x70,
39 CX18_AV_SVIDEO_LUMA8 = 0x80,
40 CX18_AV_SVIDEO_CHROMA4 = 0x400,
41 CX18_AV_SVIDEO_CHROMA5 = 0x500,
[all …]
H A Dcx18-av-core.c17 u32 reg = 0xc40000 + (addr & ~3); in cx18_av_write()
18 u32 mask = 0xff; in cx18_av_write()
24 return 0; in cx18_av_write()
29 u32 reg = 0xc40000 + (addr & ~3); in cx18_av_write_expect()
33 x = (x & ~((u32)0xff << shift)) | ((u32)value << shift); in cx18_av_write_expect()
36 return 0; in cx18_av_write_expect()
41 cx18_write_reg(cx, value, 0xc40000 + addr); in cx18_av_write4()
42 return 0; in cx18_av_write4()
48 cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask); in cx18_av_write4_expect()
49 return 0; in cx18_av_write4_expect()
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dradio.c30 0x0002, 0x0003, 0x0001, 0x000F,
31 0x0006, 0x0007, 0x0005, 0x000F,
32 0x000A, 0x000B, 0x0009, 0x000F,
33 0x000E, 0x000F, 0x000D, 0x000F,
41 u16 flipped = 0x0000; in flip_4bit()
43 B43legacy_BUG_ON(!((value & ~0x000F) == 0x0000)); in flip_4bit()
45 flipped |= (value & 0x0001) << 3; in flip_4bit()
46 flipped |= (value & 0x0002) << 1; in flip_4bit()
47 flipped |= (value & 0x0004) >> 1; in flip_4bit()
48 flipped |= (value & 0x0008) >> 3; in flip_4bit()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_d.h27 #define mmIH_VMID_0_LUT 0xf50
28 #define mmIH_VMID_1_LUT 0xf51
29 #define mmIH_VMID_2_LUT 0xf52
30 #define mmIH_VMID_3_LUT 0xf53
31 #define mmIH_VMID_4_LUT 0xf54
32 #define mmIH_VMID_5_LUT 0xf55
33 #define mmIH_VMID_6_LUT 0xf56
34 #define mmIH_VMID_7_LUT 0xf57
35 #define mmIH_VMID_8_LUT 0xf58
36 #define mmIH_VMID_9_LUT 0xf59
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Ddc.h12 /* CMD register 0x000 ~ 0x43 */
14 /* Address 0x000 ~ 0x002 */
21 /* Address 0x008 ~ 0x00a */
28 /* Address 0x010 ~ 0x012 */
35 /* Address 0x018 ~ 0x01a */
42 /* Address 0x028 */
47 /* Address 0x030 ~ 0x033 */
55 /* Address 0x036 ~ 0x03e */
68 /* Address 0x040 ~ 0x043 */
80 /* COM register 0x300 ~ 0x329 */
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Dtable.c8 0x800, 0x80040000,
9 0x804, 0x00000003,
10 0x808, 0x0000FC00,
11 0x80C, 0x0000000A,
12 0x810, 0x10001331,
13 0x814, 0x020C3D10,
14 0x818, 0x02200385,
15 0x81C, 0x00000000,
16 0x820, 0x01000100,
17 0x824, 0x00190204,
[all …]
/openbmc/linux/drivers/ata/
H A Dsata_qstor.c39 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
40 QS_HID_HPHY = 0x0004, /* host physical interface info */
41 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
42 QS_HST_SFF = 0x0100, /* host status fifo offset */
43 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
47 QS_CNFG3_GSRST = 0x01, /* global chip reset */
48 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
51 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
52 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
53 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
[all …]
/openbmc/linux/drivers/gpu/drm/tegra/
H A Ddc.h176 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000
177 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
179 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
180 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
181 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008
182 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
183 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
184 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010
185 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
186 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8723d_table.c10 0x020, 0x00000013,
11 0x02F, 0x00000010,
12 0x077, 0x00000007,
13 0x421, 0x0000000F,
14 0x428, 0x0000000A,
15 0x429, 0x00000010,
16 0x430, 0x00000000,
17 0x431, 0x00000000,
18 0x432, 0x00000000,
19 0x433, 0x00000001,
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8188f.c34 {0x024, 0xDF}, {0x025, 0x07}, {0x02B, 0x1C}, {0x283, 0x20},
35 {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00},
36 {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04},
37 {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04},
38 {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D},
39 {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00},
40 {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0},
41 {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00},
42 {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0},
43 {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x44},
[all …]
H A Drtl8xxxu_8188e.c36 {0x026, 0x41}, {0x027, 0x35}, {0x040, 0x00}, {0x421, 0x0f},
37 {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x01},
38 {0x432, 0x02}, {0x433, 0x04}, {0x434, 0x05}, {0x435, 0x06},
39 {0x436, 0x07}, {0x437, 0x08}, {0x438, 0x00}, {0x439, 0x00},
40 {0x43a, 0x01}, {0x43b, 0x02}, {0x43c, 0x04}, {0x43d, 0x05},
41 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
42 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
43 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
44 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x480, 0x08},
45 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff},
[all …]
H A Drtl8xxxu_8710b.c34 {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00},
35 {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04},
36 {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04},
37 {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D},
38 {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00},
39 {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0},
40 {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00},
41 {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0},
42 {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x66},
43 {0x461, 0x66}, {0x4C8, 0xFF}, {0x4C9, 0x08}, {0x4CC, 0xFF},
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm630.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
48 #size-cells = <0>;
53 reg = <0x0 0x100>;
73 reg = <0x0 0x101>;
88 reg = <0x0 0x102>;
103 reg = <0x0 0x103>;
115 CPU4: cpu@0 {
118 reg = <0x0 0x0>;
138 reg = <0x0 0x1>;
[all …]
H A Dsm6115.dtsi27 #clock-cells = <0>;
32 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
44 clocks = <&cpufreq_hw 0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
62 reg = <0x0 0x1>;
63 clocks = <&cpufreq_hw 0>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dwm8996.h29 #define WM8996_SOFTWARE_RESET 0x00
30 #define WM8996_POWER_MANAGEMENT_1 0x01
31 #define WM8996_POWER_MANAGEMENT_2 0x02
32 #define WM8996_POWER_MANAGEMENT_3 0x03
33 #define WM8996_POWER_MANAGEMENT_4 0x04
34 #define WM8996_POWER_MANAGEMENT_5 0x05
35 #define WM8996_POWER_MANAGEMENT_6 0x06
36 #define WM8996_POWER_MANAGEMENT_7 0x07
37 #define WM8996_POWER_MANAGEMENT_8 0x08
38 #define WM8996_LEFT_LINE_INPUT_VOLUME 0x10
[all …]
H A Dwm8995.h18 #define WM8995_SOFTWARE_RESET 0x00
19 #define WM8995_POWER_MANAGEMENT_1 0x01
20 #define WM8995_POWER_MANAGEMENT_2 0x02
21 #define WM8995_POWER_MANAGEMENT_3 0x03
22 #define WM8995_POWER_MANAGEMENT_4 0x04
23 #define WM8995_POWER_MANAGEMENT_5 0x05
24 #define WM8995_LEFT_LINE_INPUT_1_VOLUME 0x10
25 #define WM8995_RIGHT_LINE_INPUT_1_VOLUME 0x11
26 #define WM8995_LEFT_LINE_INPUT_CONTROL 0x12
27 #define WM8995_DAC1_LEFT_VOLUME 0x18
[all …]
H A Dwm5100.h26 #define WM5100_CLKSRC_MCLK1 0
34 #define WM5100_CLKSRC_ASYNCCLK 0x100
39 #define WM5100_FLL_SRC_MCLK1 0x0
40 #define WM5100_FLL_SRC_MCLK2 0x1
41 #define WM5100_FLL_SRC_FLL1 0x4
42 #define WM5100_FLL_SRC_FLL2 0x5
43 #define WM5100_FLL_SRC_AIF1BCLK 0x8
44 #define WM5100_FLL_SRC_AIF2BCLK 0x9
45 #define WM5100_FLL_SRC_AIF3BCLK 0xa
50 #define WM5100_SOFTWARE_RESET 0x00
[all …]
/openbmc/linux/include/linux/mfd/madera/
H A Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
/openbmc/linux/drivers/media/usb/cx231xx/
H A Dcx231xx-reg.h17 #define SAV_ACTIVE_VIDEO_FIELD1 0x80
18 #define EAV_ACTIVE_VIDEO_FIELD1 0x90
20 #define SAV_ACTIVE_VIDEO_FIELD2 0xc0
21 #define EAV_ACTIVE_VIDEO_FIELD2 0xd0
23 #define SAV_VBLANK_FIELD1 0xa0
24 #define EAV_VBLANK_FIELD1 0xb0
26 #define SAV_VBLANK_FIELD2 0xe0
27 #define EAV_VBLANK_FIELD2 0xf0
29 #define SAV_VBI_FIELD1 0x20
30 #define EAV_VBI_FIELD1 0x30
[all …]
/openbmc/linux/include/linux/mfd/wm8994/
H A Dregisters.h16 #define WM8994_SOFTWARE_RESET 0x00
17 #define WM8994_POWER_MANAGEMENT_1 0x01
18 #define WM8994_POWER_MANAGEMENT_2 0x02
19 #define WM8994_POWER_MANAGEMENT_3 0x03
20 #define WM8994_POWER_MANAGEMENT_4 0x04
21 #define WM8994_POWER_MANAGEMENT_5 0x05
22 #define WM8994_POWER_MANAGEMENT_6 0x06
23 #define WM8994_INPUT_MIXER_1 0x15
24 #define WM8994_LEFT_LINE_INPUT_1_2_VOLUME 0x18
25 #define WM8994_LEFT_LINE_INPUT_3_4_VOLUME 0x19
[all …]

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