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/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dcpu.h12 #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
13 #define SSP0_BASE 0x20084000 /* SSP0 registers base */
14 #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */
15 #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
16 #define DMA_BASE 0x31000000 /* DMA controller registers base */
17 #define USB_BASE 0x31020000 /* USB registers base */
18 #define LCD_BASE 0x31040000 /* LCD registers base */
19 #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */
20 #define EMC_BASE 0x31080000 /* EMC configuration registers base */
23 #define CLK_PM_BASE 0x40004000 /* System control registers base */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dstm32-dwmac.yaml113 reg = <0x5800a000 0x2000>;
127 st,syscon = <&syscfg 0x4>;
138 reg = <0x40028000 0x8000>;
140 interrupts = <0 61 0>, <0 62 0>;
143 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
144 st,syscon = <&syscfg 0x4>;
154 reg = <0x40028000 0x8000>;
160 st,syscon = <&syscfg 0x4>;
/openbmc/linux/arch/arm/include/debug/
H A Dvf.S6 #define VF_UART0_BASE_ADDR 0x40027000
7 #define VF_UART1_BASE_ADDR 0x40028000
8 #define VF_UART2_BASE_ADDR 0x40029000
9 #define VF_UART3_BASE_ADDR 0x4002a000
14 #define VF_UART_VIRTUAL_BASE 0xfe000000
18 and \rv, \rp, #0xffffff @ offset within 16MB section
23 strb \rd, [\rx, #0x7] @ Data Register
27 1001: ldrb \rd, [\rx, #0x4] @ Status Register 1
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio_lpc32xx.txt9 0: GPIO P0
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
24 reg = <0x40028000 0x1000>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dvf610-clock.txt29 reg = <0x4006b000 0x1000>;
37 reg = <0x40028000 0x1000>;
38 interrupts = <0 62 0x04>;
/openbmc/u-boot/arch/arm/dts/
H A Dvf.dtsi37 reg = <0x40000000 0x00070000>;
42 reg = <0x40027000 0x1000>;
48 reg = <0x40028000 0x1000>;
54 reg = <0x40029000 0x1000>;
60 reg = <0x4002a000 0x1000>;
66 #size-cells = <0>;
68 reg = <0x4002c000 0x1000>;
75 #size-cells = <0>;
77 reg = <0x4002d000 0x1000>;
84 #size-cells = <0>;
[all …]
H A Dstm32f746.dtsi56 #clock-cells = <0>;
58 clock-frequency = <0>;
66 reg = <0x40028000 0x8000>;
68 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
69 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
70 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
81 reg = <0xA0000000 0x1000>;
82 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
89 #size-cells = <0>;
90 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
[all …]
H A Dstm32f429.dtsi52 #clock-cells = <0>;
54 clock-frequency = <0>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
72 clock-frequency = <0>;
79 reg = <0x40000000 0x400>;
81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
87 #size-cells = <0>;
89 reg = <0x40000000 0x400>;
[all …]
/openbmc/qemu/hw/arm/
H A Dstm32f405_soc.c33 #define RCC_ADDR 0x40023800
34 #define SYSCFG_ADD 0x40013800
35 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
36 0x40004C00, 0x40005000, 0x40011400,
37 0x40007800, 0x40007C00 };
39 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
40 0x40000800, 0x40000C00 };
41 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200,
42 0x40012300, 0x40012400, 0x40012500 };
43 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
[all …]
H A Dmps2.c130 memory_region_init_alias(mr, NULL, name, orig, 0, in make_ram_alias()
166 * 0x21000000 .. 0x21ffffff : PSRAM (16MB) in mps2_common_init()
168 * 0x00000000 .. 0x003fffff : ZBT SSRAM1 in mps2_common_init()
169 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 in mps2_common_init()
170 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 in mps2_common_init()
171 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 in mps2_common_init()
173 * 0x01000000 .. 0x01003fff : block RAM (16K) in mps2_common_init()
174 * 0x01004000 .. 0x01007fff : mirror of above in mps2_common_init()
175 * 0x01008000 .. 0x0100bfff : mirror of above in mps2_common_init()
176 * 0x0100c000 .. 0x0100ffff : mirror of above in mps2_common_init()
[all …]
H A Dstellaris.c37 #define GPIO_A 0
45 #define BP_OLED_I2C 0x01
46 #define BP_OLED_SSI 0x02
47 #define BP_GAMEPAD 0x04
101 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); in ssys_update()
105 0x31c0, /* 1 Mhz */
106 0x1ae0, /* 1.8432 Mhz */
107 0x18c0, /* 2 Mhz */
108 0xd573, /* 2.4576 Mhz */
109 0x37a6, /* 3.57954 Mhz */
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
/openbmc/linux/arch/arm/mach-lpc32xx/
H A Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32f429.dtsi58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 #size-cells = <0>;
[all …]
H A Dstm32h743.dtsi54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
68 clock-frequency = <0>;
75 reg = <0x40000c00 0x400>;
82 #size-cells = <0>;
84 reg = <0x40002400 0x400>;
95 trigger@0 {
97 reg = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/vf/
H A Dvfxxx.dtsi33 #clock-cells = <0>;
39 #clock-cells = <0>;
46 offset = <0x0>;
47 mask = <0x1000>;
66 reg = <0x40000000 0x00070000>;
71 reg = <0x40001000 0x800>;
76 reg = <0x40001800 0x400>;
85 reg = <0x40018000 0x2000>,
86 <0x40024000 0x1000>,
87 <0x40025000 0x1000>;
[all …]
/openbmc/linux/arch/arm/
H A DKconfig.debug149 0x80000000 | 0xf0000000 | UART0
150 0x80004000 | 0xf0004000 | UART1
151 0x80008000 | 0xf0008000 | UART2
152 0x8000c000 | 0xf000c000 | UART3
153 0x80010000 | 0xf0010000 | UART4
154 0x80014000 | 0xf0014000 | UART5
155 0x80018000 | 0xf0018000 | UART6
156 0x8001c000 | 0xf001c000 | UART7
157 0x80020000 | 0xf0020000 | UART8
158 0x80024000 | 0xf0024000 | UART9
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/skylake/
H A Dcache.json4 "EventCode": "0x51",
8 "UMask": "0x1"
12 "EventCode": "0x48",
16 "UMask": "0x2"
20 "EventCode": "0x48",
24 "UMask": "0x1"
29 "EventCode": "0x48",
33 "UMask": "0x1"
39 "EventCode": "0x48",
42 "UMask": "0x1"
[all …]