1*e92935e1SRoland StiggeNXP LPC32xx SoC GPIO controller 2*e92935e1SRoland Stigge 3*e92935e1SRoland StiggeRequired properties: 4*e92935e1SRoland Stigge- compatible: must be "nxp,lpc3220-gpio" 5*e92935e1SRoland Stigge- reg: Physical base address and length of the controller's registers. 6*e92935e1SRoland Stigge- gpio-controller: Marks the device node as a GPIO controller. 7*e92935e1SRoland Stigge- #gpio-cells: Should be 3: 8*e92935e1SRoland Stigge 1) bank: 9*e92935e1SRoland Stigge 0: GPIO P0 10*e92935e1SRoland Stigge 1: GPIO P1 11*e92935e1SRoland Stigge 2: GPIO P2 12*e92935e1SRoland Stigge 3: GPIO P3 13*e92935e1SRoland Stigge 4: GPI P3 14*e92935e1SRoland Stigge 5: GPO P3 15*e92935e1SRoland Stigge 2) pin number 16*e92935e1SRoland Stigge 3) optional parameters: 17*e92935e1SRoland Stigge - bit 0 specifies polarity (0 for normal, 1 for inverted) 18*e92935e1SRoland Stigge- reg: Index of the GPIO group 19*e92935e1SRoland Stigge 20*e92935e1SRoland StiggeExample: 21*e92935e1SRoland Stigge 22*e92935e1SRoland Stigge gpio: gpio@40028000 { 23*e92935e1SRoland Stigge compatible = "nxp,lpc3220-gpio"; 24*e92935e1SRoland Stigge reg = <0x40028000 0x1000>; 25*e92935e1SRoland Stigge gpio-controller; 26*e92935e1SRoland Stigge #gpio-cells = <3>; /* bank, pin, flags */ 27*e92935e1SRoland Stigge }; 28*e92935e1SRoland Stigge 29*e92935e1SRoland Stigge leds { 30*e92935e1SRoland Stigge compatible = "gpio-leds"; 31*e92935e1SRoland Stigge 32*e92935e1SRoland Stigge led0 { 33*e92935e1SRoland Stigge gpios = <&gpio 5 1 1>; /* GPO_P3 1, active low */ 34*e92935e1SRoland Stigge linux,default-trigger = "heartbeat"; 35*e92935e1SRoland Stigge default-state = "off"; 36*e92935e1SRoland Stigge }; 37*e92935e1SRoland Stigge 38*e92935e1SRoland Stigge led1 { 39*e92935e1SRoland Stigge gpios = <&gpio 5 14 1>; /* GPO_P3 14, active low */ 40*e92935e1SRoland Stigge linux,default-trigger = "timer"; 41*e92935e1SRoland Stigge default-state = "off"; 42*e92935e1SRoland Stigge }; 43*e92935e1SRoland Stigge }; 44