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/openbmc/u-boot/include/configs/
H A DM54455EVB.h23 #define CONFIG_SYS_UART_PORT (0)
44 # define CONFIG_SYS_FEC0_PINMUX 0
45 # define CONFIG_SYS_FEC1_PINMUX 0
71 #define CONFIG_SYS_LOAD_ADDR2 0x40010013
73 "netdev=eth0\0" \
74 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
75 "loadaddr=0x40010000\0" \
76 "sbfhdr=sbfhdr.bin\0" \
77 "uboot=u-boot.bin\0" \
79 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
[all …]
H A DM5373EVB.h22 #define CONFIG_SYS_UART_PORT (0)
36 # define CONFIG_SYS_FEC0_PINMUX 0
61 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
62 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
76 "netdev=eth0\0" \
77 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
78 "u-boot=u-boot.bin\0" \
79 "load=tftp ${loadaddr) ${u-boot}\0" \
80 "upd=run load; run prog\0" \
81 "prog=prot off 0 3ffff;" \
[all …]
H A DM5329EVB.h22 #define CONFIG_SYS_UART_PORT (0)
36 # define CONFIG_SYS_FEC0_PINMUX 0
61 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
62 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
76 "netdev=eth0\0" \
77 "loadaddr=40010000\0" \
78 "u-boot=u-boot.bin\0" \
79 "load=tftp ${loadaddr) ${u-boot}\0" \
80 "upd=run load; run prog\0" \
81 "prog=prot off 0 3ffff;" \
[all …]
H A DM52277EVB.h22 #define CONFIG_SYS_UART_PORT (0)
34 #define CONFIG_SYS_UBOOT_END 0x3FFFF
35 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
39 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
40 "loadaddr=0x40010000\0" \
41 "uboot=u-boot.bin\0" \
43 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
44 "upd=run load; run prog\0" \
45 "prog=sf probe 0:2 10000 1;" \
46 "sf erase 0 30000;" \
[all …]
H A DM54418TWR.h22 #define CONFIG_SYS_UART_PORT (0)
42 #define CONFIG_SYS_NAND_BASE 0xFC0FC000
58 #define CONFIG_SYS_FEC0_PINMUX 0
60 #define CONFIG_SYS_FEC1_PINMUX 0
63 #define CONFIG_SYS_FEC0_PHYADDR 0
79 #define LINKSTATUS 0
90 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
92 "netdev=eth0\0" \
93 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
94 "loadaddr=0x40010000\0" \
[all …]
H A DM5208EVBE.h17 #define CONFIG_SYS_UART_PORT (0)
30 # define CONFIG_SYS_FEC0_PINMUX 0
52 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
53 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
67 "netdev=eth0\0" \
68 "loadaddr=40010000\0" \
69 "u-boot=u-boot.bin\0" \
70 "load=tftp ${loadaddr) ${u-boot}\0" \
71 "upd=run load; run prog\0" \
72 "prog=prot off 0 3ffff;" \
[all …]
H A DM53017EVB.h22 #define CONFIG_SYS_UART_PORT (0)
39 # define CONFIG_SYS_FEC0_PINMUX 0
41 # define CONFIG_SYS_FEC1_PINMUX 0
58 #define CONFIG_SYS_RTC_CNT (0x8000)
69 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
70 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
84 "netdev=eth0\0" \
85 "loadaddr=40010000\0" \
86 "u-boot=u-boot.bin\0" \
87 "load=tftp ${loadaddr) ${u-boot}\0" \
[all …]
H A DM54451EVB.h23 #define CONFIG_SYS_UART_PORT (0)
44 # define CONFIG_SYS_FEC0_PINMUX 0
68 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
70 "netdev=eth0\0" \
71 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
72 "loadaddr=0x40010000\0" \
73 "sbfhdr=sbfhdr.bin\0" \
74 "uboot=u-boot.bin\0" \
76 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
77 "upd=run load; run prog\0" \
[all …]
H A DM5485EVB.h22 #define CONFIG_SYS_UART_PORT (0)
40 # define CONFIG_SYS_FEC0_PINMUX 0
42 # define CONFIG_SYS_FEC1_PINMUX 0
66 # define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000
76 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
77 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
84 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000
86 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
88 #define CONFIG_SYS_PCI_IO_BUS 0x71000000
90 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
[all …]
H A DM5475EVB.h22 #define CONFIG_SYS_UART_PORT (0)
40 # define CONFIG_SYS_FEC0_PINMUX 0
42 # define CONFIG_SYS_FEC1_PINMUX 0
79 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
80 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
89 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000
91 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
93 #define CONFIG_SYS_PCI_IO_BUS 0x71000000
95 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
97 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dnxp,lpc1850-dwmac.txt13 reg = <0x40010000 0x2000>;
H A Dsnps,dwc-qos-ethernet.txt125 - #size-cells: Must be <0>.
143 interrupts = <0x0 0x1e 0x4>;
144 reg = <0x40010000 0x4000>;
153 snps,burst-map = <0x7>;
160 #address-cells = <0x1>;
161 #size-cells = <0x0>;
165 reg = <0x1>;
/openbmc/u-boot/configs/
H A Dls1021aiot_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x40010000
/openbmc/u-boot/arch/arm/mach-stm32mp/
H A DKconfig43 default 0xC0100000
47 DDR + 1MB (0xC0100000)
67 default 0x40010000
/openbmc/u-boot/test/lib/
H A Dlmb.c20 ut_asserteq(lmb->memory.region[0].base, ram_base); in check_lmb()
21 ut_asserteq(lmb->memory.region[0].size, ram_size); in check_lmb()
25 if (num_reserved > 0) { in check_lmb()
26 ut_asserteq(lmb->reserved.region[0].base, base1); in check_lmb()
27 ut_asserteq(lmb->reserved.region[0].size, size1); in check_lmb()
37 return 0; in check_lmb()
56 const phys_addr_t alloc_64k_end = alloc_64k_addr + 0x10000; in test_multi_alloc()
63 ut_assert(ram_end == 0 || ram_end > ram); in test_multi_alloc()
73 ut_asserteq(ret, 0); in test_multi_alloc()
77 ut_asserteq(ret, 0); in test_multi_alloc()
[all …]
/openbmc/linux/arch/m68k/fpsp040/
H A Dstan.S27 | k = N mod 2, so in particular, k = 0 or 1.
62 BOUNDS1: .long 0x3FD78000,0x4004BC7E
63 TWOBYPI: .long 0x3FE45F30,0x6DC9C883
65 TANQ4: .long 0x3EA0B759,0xF50F8688
66 TANP3: .long 0xBEF2BAA5,0xA8924F04
68 TANQ3: .long 0xBF346F59,0xB39BA65F,0x00000000,0x00000000
70 TANP2: .long 0x3FF60000,0xE073D3FC,0x199C4A00,0x00000000
72 TANQ2: .long 0x3FF90000,0xD23CD684,0x15D95FA1,0x00000000
74 TANP1: .long 0xBFFC0000,0x8895A6C5,0xFB423BCA,0x00000000
76 TANQ1: .long 0xBFFD0000,0xEEF57E0D,0xA84BC8CE,0x00000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dnxp,lpc3220-mic.txt25 reg = <0x40008000 0x4000>;
32 reg = <0x4000c000 0x4000>;
37 interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
43 reg = <0x40010000 0x4000>;
55 reg = <0x40048000 0x1000>;
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dnxp,lpc1850-rgu.txt67 reg = <0x40053000 0x1000>;
76 reg = <0x40010000 0x2000>;
/openbmc/u-boot/arch/arm/mach-stm32mp/include/mach/
H A Dstm32.h13 #define STM32_RCC_BASE 0x50000000
14 #define STM32_PWR_BASE 0x50001000
15 #define STM32_DBGMCU_BASE 0x50081000
16 #define STM32_BSEC_BASE 0x5C005000
17 #define STM32_TZC_BASE 0x5C006000
18 #define STM32_ETZPC_BASE 0x5C007000
19 #define STM32_TAMP_BASE 0x5C00A000
23 #define STM32_USART1_BASE 0x5C000000
24 #define STM32_USART2_BASE 0x4000E000
25 #define STM32_USART3_BASE 0x4000F000
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear310.dtsi15 ranges = <0x40000000 0x40000000 0x10000000
16 0xb0000000 0xb0000000 0x10000000
17 0xd0000000 0xd0000000 0x30000000>;
21 reg = <0xb4000000 0x1000>;
29 reg = <0x44000000 0x1000 /* FSMC Register */
30 0x40000000 0x0010 /* NAND Base DATA */
31 0x40020000 0x0010 /* NAND Base ADDR */
32 0x40010000 0x0010>; /* NAND Base CMD */
39 reg = <0xb4000000 0x1000>;
49 ranges = <0xb0000000 0xb0000000 0x10000000
[all …]
/openbmc/qemu/hw/arm/
H A Dmps2.c130 memory_region_init_alias(mr, NULL, name, orig, 0, in make_ram_alias()
166 * 0x21000000 .. 0x21ffffff : PSRAM (16MB) in mps2_common_init()
168 * 0x00000000 .. 0x003fffff : ZBT SSRAM1 in mps2_common_init()
169 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 in mps2_common_init()
170 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 in mps2_common_init()
171 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 in mps2_common_init()
173 * 0x01000000 .. 0x01003fff : block RAM (16K) in mps2_common_init()
174 * 0x01004000 .. 0x01007fff : mirror of above in mps2_common_init()
175 * 0x01008000 .. 0x0100bfff : mirror of above in mps2_common_init()
176 * 0x0100c000 .. 0x0100ffff : mirror of above in mps2_common_init()
[all …]
/openbmc/linux/arch/x86/include/asm/
H A Dcpuid.h16 CPUID_EAX = 0,
39 : "0" (*eax), "2" (*ecx) in native_cpuid()
46 unsigned int eax = op, ebx, ecx = 0, edx; \
77 *ecx = 0; in native_cpuid_reg()
135 case 0xb: in cpuid_function_is_indexed()
136 case 0xd: in cpuid_function_is_indexed()
137 case 0xf: in cpuid_function_is_indexed()
138 case 0x10: in cpuid_function_is_indexed()
139 case 0x12: in cpuid_function_is_indexed()
140 case 0x14: in cpuid_function_is_indexed()
[all …]
/openbmc/linux/drivers/firmware/efi/
H A Dsysfb_efi.c30 OVERRIDE_NONE = 0x0,
31 OVERRIDE_BASE = 0x1,
32 OVERRIDE_STRIDE = 0x2,
33 OVERRIDE_HEIGHT = 0x4,
34 OVERRIDE_WIDTH = 0x8,
38 [M_I17] = { "i17", 0x80010000, 1472 * 4, 1440, 900, OVERRIDE_NONE },
39 [M_I20] = { "i20", 0x80010000, 1728 * 4, 1680, 1050, OVERRIDE_NONE }, /* guess */
40 [M_I20_SR] = { "imac7", 0x40010000, 1728 * 4, 1680, 1050, OVERRIDE_NONE },
41 [M_I24] = { "i24", 0x80010000, 2048 * 4, 1920, 1200, OVERRIDE_NONE }, /* guess */
42 [M_I24_8_1] = { "imac8", 0xc0060000, 2048 * 4, 1920, 1200, OVERRIDE_NONE },
[all …]
/openbmc/qemu/hw/riscv/
H A Dmicroblaze-v-generic.c30 #define MEMORY_BASEADDR 0x80000000
31 #define INTC_BASEADDR 0x41200000
32 #define TIMER_BASEADDR 0x41c00000
33 #define TIMER_BASEADDR2 0x41c10000
34 #define UARTLITE_BASEADDR 0x40600000
35 #define ETHLITE_BASEADDR 0x40e00000
36 #define UART16550_BASEADDR 0x44a10000
37 #define AXIENET_BASEADDR 0x40c00000
38 #define AXIDMA_BASEADDR 0x41e00000
39 #define GPIO_BASEADDR 0x40000000
[all …]
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dsnps,dwc-qos-ethernet.txt126 - #size-cells: Must be <0>.
141 interrupts = <0x0 0x1e 0x4>;
142 reg = <0x40010000 0x4000>;
151 snps,burst-map = <0x7>;
158 #address-cells = <0x1>;
159 #size-cells = <0x0>;
163 reg = <0x1>;

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