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Searched +full:0 +full:x20030000 (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dinno-rk3036.txt16 reg = <0x20030000 0x4000>;
/openbmc/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_cfg.h11 #define MSM_DSI_VER_MAJOR_V2 0x02
12 #define MSM_DSI_VER_MAJOR_6G 0x03
13 #define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000
14 #define MSM_DSI_6G_VER_MINOR_V1_0_2 0x10000002
15 #define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000
16 #define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001
17 #define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000
18 #define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000
19 #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001
20 #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-rockchip.yaml102 reg = <0x20030000 0x10>;
/openbmc/u-boot/arch/arm/dts/
H A Drk3xxx.dtsi40 reg = <0x20018000 0x4000>;
41 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
51 reg = <0x2001c000 0x4000>;
52 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
63 reg = <0x20078000 0x4000>;
76 #clock-cells = <0>;
82 reg = <0x10138000 0x1000>;
89 reg = <0x1013c000 0x100>;
94 reg = <0x1013c200 0x20>;
95 interrupts = <GIC_PPI 11 0x304>;
[all …]
H A Drv1108.dtsi28 #size-cells = <0>;
33 reg = <0xf00>;
53 #clock-cells = <0>;
64 reg = <0x102a0000 0x4000>;
65 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
75 reg = <0x10080000 0x2000>;
78 ranges = <0 0x10080000 0x2000>;
83 reg = <0x10210000 0x100>;
91 pinctrl-0 = <&uart2m0_xfer>;
97 reg = <0x10220000 0x100>;
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3xxx.dtsi35 #clock-cells = <0>;
41 reg = <0x10090000 0x10000>;
52 reg = <0x10104000 0x800>;
64 reg = <0x10138000 0x1000>;
71 reg = <0x1013c000 0x100>;
76 reg = <0x1013c200 0x20>;
90 reg = <0x1013c600 0x20>;
99 reg = <0x1013d000 0x1000>,
100 <0x1013c100 0x0100>;
105 reg = <0x10124000 0x400>;
[all …]
H A Drk3036.dtsi34 #size-cells = <0>;
40 reg = <0xf00>;
53 reg = <0xf01>;
84 #clock-cells = <0>;
89 reg = <0x10080000 0x2000>;
92 ranges = <0 0x10080000 0x2000>;
94 smp-sram@0 {
96 reg = <0x00 0x10>;
102 reg = <0x10090000 0x10000>;
122 reg = <0x10108000 0x800>;
[all …]
H A Drv1108.dtsi29 #size-cells = <0>;
34 reg = <0xf00>;
43 cpu_opp_table: opp-table-0 {
85 #clock-cells = <0>;
90 reg = <0x10080000 0x2000>;
93 ranges = <0 0x10080000 0x2000>;
98 reg = <0x10210000 0x100>;
107 pinctrl-0 = <&uart2m0_xfer>;
113 reg = <0x10220000 0x100>;
122 pinctrl-0 = <&uart1_xfer>;
[all …]
H A Drk322x.dtsi26 #size-cells = <0>;
31 reg = <0xf00>;
43 reg = <0xf01>;
53 reg = <0xf02>;
63 reg = <0xf03>;
71 cpu0_opp_table: opp-table-0 {
127 #clock-cells = <0>;
137 reg = <0x100b0000 0x4000>;
144 pinctrl-0 = <&i2s1_bus>;
150 reg = <0x100c0000 0x4000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15_a7.dts16 arm,hbi = <0x249>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0>;
61 reg = <0x100>;
71 reg = <0x101>;
81 reg = <0x102>;
109 reg = <0 0x80000000 0 0x40000000>;
117 /* Chipselect 2 is physically at 0x18000000 */
[all …]
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi12 reg = <0x0 0x2a810000 0x0 0x10000>;
16 ranges = <0 0x0 0x2a820000 0x20000>;
21 reg = <0x10000 0x10000>;
27 reg = <0x0 0x2b1f0000 0x0 0x1000>;
38 reg = <0x0 0x2b400000 0x0 0x10000>;
50 reg = <0x0 0x2b500000 0x0 0x10000>;
61 reg = <0x0 0x2b600000 0x0 0x10000>;
67 power-domains = <&scpi_devpd 0>;
72 reg = <0x0 0x2c010000 0 0x1000>,
73 <0x0 0x2c02f000 0 0x2000>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62a-main.dtsi11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
21 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
22 <0x01 0x00000000 0x00 0x2000>, /* GICC */
23 <0x01 0x00010000 0x00 0x1000>, /* GICH */
24 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
[all …]
H A Dk3-am62-main.dtsi11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
27 <0x01 0x00000000 0x00 0x2000>, /* GICC */
28 <0x01 0x00010000 0x00 0x1000>, /* GICH */
29 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
[all …]
H A Dk3-am64-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x00 0x70000000 0x00 0x200000>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
28 reg = <0x1c0000 0x20000>;
32 reg = <0x1e0000 0x1c000>;
36 reg = <0x1fc000 0x4000>;
42 reg = <0x0 0x43000000 0x0 0x20000>;
45 ranges = <0x0 0x0 0x43000000 0x20000>;
49 reg = <0x00000014 0x4>;
[all …]