dts/ti/k3-am62a-main.dtsi

11 		reg = <0x00 0x70000000 0x00 0x10000>;
14 		ranges = <0x0 0x00 0x70000000 0x10000>;
19 		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
20 		      <0x00 0x01880000 0x00 0xc0000>,	/* GICR */
21 		      <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
22 		      <0x01 0x00000000 0x00 0x2000>,    /* GICC */
23 		      <0x01 0x00010000 0x00 0x1000>,    /* GICH */
24 		      <0x01 0x00020000 0x00 0x2000>;    /* GICV */
38 			reg = <0x00 0x01820000 0x00 0x10000>;
39 			socionext,synquacer-pre-its = <0x1000000 0x400000>;
47 		reg = <0x00 0x00100000 0x00 0x20000>;
50 		ranges = <0x00 0x00 0x00100000 0x20000>;
54 			reg = <0x4044 0x8>;
60 			reg = <0x4130 0x4>;
70 		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
76 			reg = <0x00 0x4d000000 0x00 0x80000>,
77 			      <0x00 0x4a600000 0x00 0x80000>,
78 			      <0x00 0x4a400000 0x00 0x80000>;
87 			reg = <0x00 0x48000000 0x00 0x100000>;
88 			#interrupt-cells = <0>;
100 			reg = <0x00 0x485c0100 0x00 0x100>,
101 			      <0x00 0x4c000000 0x00 0x20000>,
102 			      <0x00 0x4a820000 0x00 0x20000>,
103 			      <0x00 0x4aa40000 0x00 0x20000>,
104 			      <0x00 0x4bc00000 0x00 0x100000>;
110 			ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
111 			ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
112 			ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
117 			reg = <0x00 0x485c0000 0x00 0x100>,
118 			      <0x00 0x4a800000 0x00 0x20000>,
119 			      <0x00 0x4aa00000 0x00 0x40000>,
120 			      <0x00 0x4b800000 0x00 0x400000>;
126 			ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
127 						<0x24>, /* CPSW_TX_CHAN */
128 						<0x25>, /* SAUL_TX_0_CHAN */
129 						<0x26>; /* SAUL_TX_1_CHAN */
130 			ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
131 						<0x11>, /* RING_CPSW_TX_CHAN */
132 						<0x12>, /* RING_SAUL_TX_0_CHAN */
133 						<0x13>; /* RING_SAUL_TX_1_CHAN */
134 			ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
135 						<0x2b>, /* CPSW_RX_CHAN */
136 						<0x2d>, /* SAUL_RX_0_CHAN */
137 						<0x2f>, /* SAUL_RX_1_CHAN */
138 						<0x31>, /* SAUL_RX_2_CHAN */
139 						<0x33>; /* SAUL_RX_3_CHAN */
140 			ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
141 						<0x2c>, /* FLOW_CPSW_RX_CHAN */
142 						<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
143 						<0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
149 		reg = <0x00 0x44043000 0x00 0xfe0>;
176 		reg = <0x00 0x43600000 0x00 0x10000>,
177 		      <0x00 0x44880000 0x00 0x20000>,
178 		      <0x00 0x44860000 0x00 0x20000>;
189 		reg = <0x00 0xf4000 0x00 0x2ac>;
192 		pinctrl-single,function-mask = <0xffffffff>;
197 		reg = <0x00 0x2400000 0x00 0x400>;
209 		reg = <0x00 0x2410000 0x00 0x400>;
221 		reg = <0x00 0x2420000 0x00 0x400>;
233 		reg = <0x00 0x2430000 0x00 0x400>;
245 		reg = <0x00 0x2440000 0x00 0x400>;
257 		reg = <0x00 0x2450000 0x00 0x400>;
269 		reg = <0x00 0x2460000 0x00 0x400>;
281 		reg = <0x00 0x2470000 0x00 0x400>;
293 		reg = <0x00 0x02800000 0x00 0x100>;
296 		clocks = <&k3_clks 146 0>;
303 		reg = <0x00 0x02810000 0x00 0x100>;
306 		clocks = <&k3_clks 152 0>;
313 		reg = <0x00 0x02820000 0x00 0x100>;
316 		clocks = <&k3_clks 153 0>;
323 		reg = <0x00 0x02830000 0x00 0x100>;
326 		clocks = <&k3_clks 154 0>;
333 		reg = <0x00 0x02840000 0x00 0x100>;
336 		clocks = <&k3_clks 155 0>;
343 		reg = <0x00 0x02850000 0x00 0x100>;
346 		clocks = <&k3_clks 156 0>;
353 		reg = <0x00 0x02860000 0x00 0x100>;
356 		clocks = <&k3_clks 158 0>;
363 		reg = <0x00 0x20000000 0x00 0x100>;
366 		#size-cells = <0>;
375 		reg = <0x00 0x20010000 0x00 0x100>;
378 		#size-cells = <0>;
387 		reg = <0x00 0x20020000 0x00 0x100>;
390 		#size-cells = <0>;
399 		reg = <0x00 0x20030000 0x00 0x100>;
402 		#size-cells = <0>;
411 		reg = <0x00 0x20100000 0x00 0x400>;
414 		#size-cells = <0>;
416 		clocks = <&k3_clks 141 0>;
422 		reg = <0x00 0x20110000 0x00 0x400>;
425 		#size-cells = <0>;
427 		clocks = <&k3_clks 142 0>;
433 		reg = <0x00 0x20120000 0x00 0x400>;
436 		#size-cells = <0>;
438 		clocks = <&k3_clks 143 0>;
444 		reg = <0x00 0x00a00000 0x00 0x800>;
451 		ti,interrupt-ranges = <0 32 16>;
457 		reg = <0x00 0x00600000 0x0 0x100>;
466 		ti,davinci-gpio-unbanked = <0>;
468 		clocks = <&k3_clks 77 0>;
475 		reg = <0x00 0x00601000 0x0 0x100>;
484 		ti,davinci-gpio-unbanked = <0>;
486 		clocks = <&k3_clks 78 0>;
493 		reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
498 		ti,trm-icp = <0x2>;
499 		ti,otap-del-sel-legacy = <0x0>;
500 		ti,otap-del-sel-sd-hs = <0x0>;
501 		ti,otap-del-sel-sdr12 = <0xf>;
502 		ti,otap-del-sel-sdr25 = <0xf>;
503 		ti,otap-del-sel-sdr50 = <0xc>;
504 		ti,otap-del-sel-sdr104 = <0x6>;
505 		ti,otap-del-sel-ddr50 = <0x9>;
506 		ti,itap-del-sel-legacy = <0x0>;
507 		ti,itap-del-sel-sd-hs = <0x0>;
508 		ti,itap-del-sel-sdr12 = <0x0>;
509 		ti,itap-del-sel-sdr25 = <0x0>;
510 		ti,clkbuf-sel = <0x7>;
518 		reg = <0x00 0x0f900000 0x00 0x800>;
521 		ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
530 			reg = <0x00 0x31000000 0x00 0x50000>;
531 			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
532 				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
541 		reg = <0x00 0x0f910000 0x00 0x800>;
544 		ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
553 			reg = <0x00 0x31100000 0x00 0x50000>;
554 			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
555 				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
564 		reg = <0x00 0x0fc00000 0x00 0x70000>;
572 			reg = <0x00 0x0fc40000 0x00 0x100>,
573 			      <0x05 0x00000000 0x01 0x00000000>;
577 			cdns,trigger-address = <0x0>;
584 			#size-cells = <0>;
592 		reg = <0x0 0x8000000 0x0 0x200000>;
594 		ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
595 		clocks = <&k3_clks 13 0>;
602 		dmas = <&main_pktdma 0xc600 15>,
603 		       <&main_pktdma 0xc601 15>,
604 		       <&main_pktdma 0xc602 15>,
605 		       <&main_pktdma 0xc603 15>,
606 		       <&main_pktdma 0xc604 15>,
607 		       <&main_pktdma 0xc605 15>,
608 		       <&main_pktdma 0xc606 15>,
609 		       <&main_pktdma 0xc607 15>,
610 		       <&main_pktdma 0x4600 15>;
616 			#size-cells = <0>;
624 				ti,syscon-efuse = <&wkup_conf 0x200>;
638 			reg = <0x0 0xf00 0x0 0x100>;
640 			#size-cells = <0>;
641 			clocks = <&k3_clks 13 0>;
648 			reg = <0x0 0x3d000 0x0 0x400>;
660 		reg = <0x00 0x2a000000 0x00 0x1000>;
666 		reg = <0x00 0x29000000 0x00 0x200>;
675 		reg = <0x00 0x29010000 0x00 0x200>;
684 		reg = <0x00 0x29020000 0x00 0x200>;
693 		reg = <0x00 0x29030000 0x00 0x200>;
702 		reg = <0x00 0x20701000 0x00 0x200>,
703 		      <0x00 0x20708000 0x00 0x8000>;
711 		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
717 		reg = <0x00 0x0e000000 0x00 0x100>;
718 		clocks = <&k3_clks 125 0>;
720 		assigned-clocks = <&k3_clks 125 0>;
726 		reg = <0x00 0x0e010000 0x00 0x100>;
727 		clocks = <&k3_clks 126 0>;
729 		assigned-clocks = <&k3_clks 126 0>;
735 		reg = <0x00 0x0e020000 0x00 0x100>;
736 		clocks = <&k3_clks 127 0>;
738 		assigned-clocks = <&k3_clks 127 0>;
744 		reg = <0x00 0x0e030000 0x00 0x100>;
745 		clocks = <&k3_clks 128 0>;
747 		assigned-clocks = <&k3_clks 128 0>;
753 		reg = <0x00 0x0e040000 0x00 0x100>;
754 		clocks = <&k3_clks 205 0>;
756 		assigned-clocks = <&k3_clks 205 0>;
763 		reg = <0x00 0x23000000 0x00 0x100>;
765 		clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
773 		reg = <0x00 0x23010000 0x00 0x100>;
775 		clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
783 		reg = <0x00 0x23020000 0x00 0x100>;
785 		clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
793 		reg = <0x00 0x23100000 0x00 0x100>;
795 		clocks = <&k3_clks 51 0>;
803 		reg = <0x00 0x23110000 0x00 0x100>;
805 		clocks = <&k3_clks 52 0>;
813 		reg = <0x00 0x23120000 0x00 0x100>;
815 		clocks = <&k3_clks 53 0>;