1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM625 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 #interrupt-cells = <3>; 23 interrupt-controller; 24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 26 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 27 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 28 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 29 /* 30 * vcpumntirq: 31 * virtual CPU interface maintenance interrupt 32 */ 33 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 34 35 gic_its: msi-controller@1820000 { 36 compatible = "arm,gic-v3-its"; 37 reg = <0x00 0x01820000 0x00 0x10000>; 38 socionext,synquacer-pre-its = <0x1000000 0x400000>; 39 msi-controller; 40 #msi-cells = <1>; 41 }; 42 }; 43 44 main_conf: syscon@100000 { 45 compatible = "syscon", "simple-mfd"; 46 reg = <0x00 0x00100000 0x00 0x20000>; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 ranges = <0x0 0x00 0x00100000 0x20000>; 50 51 phy_gmii_sel: phy@4044 { 52 compatible = "ti,am654-phy-gmii-sel"; 53 reg = <0x4044 0x8>; 54 #phy-cells = <1>; 55 }; 56 57 epwm_tbclk: clock-controller@4130 { 58 compatible = "ti,am62-epwm-tbclk"; 59 reg = <0x4130 0x4>; 60 #clock-cells = <1>; 61 }; 62 63 audio_refclk0: clock-controller@82e0 { 64 compatible = "ti,am62-audio-refclk"; 65 reg = <0x82e0 0x4>; 66 clocks = <&k3_clks 157 0>; 67 assigned-clocks = <&k3_clks 157 0>; 68 assigned-clock-parents = <&k3_clks 157 8>; 69 #clock-cells = <0>; 70 }; 71 72 audio_refclk1: clock-controller@82e4 { 73 compatible = "ti,am62-audio-refclk"; 74 reg = <0x82e4 0x4>; 75 clocks = <&k3_clks 157 10>; 76 assigned-clocks = <&k3_clks 157 10>; 77 assigned-clock-parents = <&k3_clks 157 18>; 78 #clock-cells = <0>; 79 }; 80 }; 81 82 dmss: bus@48000000 { 83 compatible = "simple-mfd"; 84 #address-cells = <2>; 85 #size-cells = <2>; 86 dma-ranges; 87 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 88 89 ti,sci-dev-id = <25>; 90 91 secure_proxy_main: mailbox@4d000000 { 92 compatible = "ti,am654-secure-proxy"; 93 #mbox-cells = <1>; 94 reg-names = "target_data", "rt", "scfg"; 95 reg = <0x00 0x4d000000 0x00 0x80000>, 96 <0x00 0x4a600000 0x00 0x80000>, 97 <0x00 0x4a400000 0x00 0x80000>; 98 interrupt-names = "rx_012"; 99 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 100 }; 101 102 inta_main_dmss: interrupt-controller@48000000 { 103 compatible = "ti,sci-inta"; 104 reg = <0x00 0x48000000 0x00 0x100000>; 105 #interrupt-cells = <0>; 106 interrupt-controller; 107 interrupt-parent = <&gic500>; 108 msi-controller; 109 ti,sci = <&dmsc>; 110 ti,sci-dev-id = <28>; 111 ti,interrupt-ranges = <4 68 36>; 112 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 113 }; 114 115 main_bcdma: dma-controller@485c0100 { 116 compatible = "ti,am64-dmss-bcdma"; 117 reg = <0x00 0x485c0100 0x00 0x100>, 118 <0x00 0x4c000000 0x00 0x20000>, 119 <0x00 0x4a820000 0x00 0x20000>, 120 <0x00 0x4aa40000 0x00 0x20000>, 121 <0x00 0x4bc00000 0x00 0x100000>; 122 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 123 msi-parent = <&inta_main_dmss>; 124 #dma-cells = <3>; 125 126 ti,sci = <&dmsc>; 127 ti,sci-dev-id = <26>; 128 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 129 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 130 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 131 }; 132 133 main_pktdma: dma-controller@485c0000 { 134 compatible = "ti,am64-dmss-pktdma"; 135 reg = <0x00 0x485c0000 0x00 0x100>, 136 <0x00 0x4a800000 0x00 0x20000>, 137 <0x00 0x4aa00000 0x00 0x40000>, 138 <0x00 0x4b800000 0x00 0x400000>; 139 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 140 msi-parent = <&inta_main_dmss>; 141 #dma-cells = <2>; 142 143 ti,sci = <&dmsc>; 144 ti,sci-dev-id = <30>; 145 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 146 <0x24>, /* CPSW_TX_CHAN */ 147 <0x25>, /* SAUL_TX_0_CHAN */ 148 <0x26>; /* SAUL_TX_1_CHAN */ 149 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 150 <0x11>, /* RING_CPSW_TX_CHAN */ 151 <0x12>, /* RING_SAUL_TX_0_CHAN */ 152 <0x13>; /* RING_SAUL_TX_1_CHAN */ 153 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 154 <0x2b>, /* CPSW_RX_CHAN */ 155 <0x2d>, /* SAUL_RX_0_CHAN */ 156 <0x2f>, /* SAUL_RX_1_CHAN */ 157 <0x31>, /* SAUL_RX_2_CHAN */ 158 <0x33>; /* SAUL_RX_3_CHAN */ 159 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 160 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 161 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 162 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 163 }; 164 }; 165 166 dmsc: system-controller@44043000 { 167 compatible = "ti,k2g-sci"; 168 ti,host-id = <12>; 169 mbox-names = "rx", "tx"; 170 mboxes = <&secure_proxy_main 12>, 171 <&secure_proxy_main 13>; 172 reg-names = "debug_messages"; 173 reg = <0x00 0x44043000 0x00 0xfe0>; 174 175 k3_pds: power-controller { 176 compatible = "ti,sci-pm-domain"; 177 #power-domain-cells = <2>; 178 }; 179 180 k3_clks: clock-controller { 181 compatible = "ti,k2g-sci-clk"; 182 #clock-cells = <2>; 183 }; 184 185 k3_reset: reset-controller { 186 compatible = "ti,sci-reset"; 187 #reset-cells = <2>; 188 }; 189 }; 190 191 crypto: crypto@40900000 { 192 compatible = "ti,am62-sa3ul"; 193 reg = <0x00 0x40900000 0x00 0x1200>; 194 #address-cells = <2>; 195 #size-cells = <2>; 196 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 197 198 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 199 <&main_pktdma 0x7507 0>; 200 dma-names = "tx", "rx1", "rx2"; 201 }; 202 203 secure_proxy_sa3: mailbox@43600000 { 204 compatible = "ti,am654-secure-proxy"; 205 #mbox-cells = <1>; 206 reg-names = "target_data", "rt", "scfg"; 207 reg = <0x00 0x43600000 0x00 0x10000>, 208 <0x00 0x44880000 0x00 0x20000>, 209 <0x00 0x44860000 0x00 0x20000>; 210 /* 211 * Marked Disabled: 212 * Node is incomplete as it is meant for bootloaders and 213 * firmware on non-MPU processors 214 */ 215 status = "disabled"; 216 }; 217 218 main_pmx0: pinctrl@f4000 { 219 compatible = "pinctrl-single"; 220 reg = <0x00 0xf4000 0x00 0x2ac>; 221 #pinctrl-cells = <1>; 222 pinctrl-single,register-width = <32>; 223 pinctrl-single,function-mask = <0xffffffff>; 224 }; 225 226 main_esm: esm@420000 { 227 compatible = "ti,j721e-esm"; 228 reg = <0x00 0x420000 0x00 0x1000>; 229 ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; 230 }; 231 232 main_timer0: timer@2400000 { 233 compatible = "ti,am654-timer"; 234 reg = <0x00 0x2400000 0x00 0x400>; 235 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&k3_clks 36 2>; 237 clock-names = "fck"; 238 assigned-clocks = <&k3_clks 36 2>; 239 assigned-clock-parents = <&k3_clks 36 3>; 240 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 241 ti,timer-pwm; 242 }; 243 244 main_timer1: timer@2410000 { 245 compatible = "ti,am654-timer"; 246 reg = <0x00 0x2410000 0x00 0x400>; 247 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&k3_clks 37 2>; 249 clock-names = "fck"; 250 assigned-clocks = <&k3_clks 37 2>; 251 assigned-clock-parents = <&k3_clks 37 3>; 252 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 253 ti,timer-pwm; 254 }; 255 256 main_timer2: timer@2420000 { 257 compatible = "ti,am654-timer"; 258 reg = <0x00 0x2420000 0x00 0x400>; 259 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&k3_clks 38 2>; 261 clock-names = "fck"; 262 assigned-clocks = <&k3_clks 38 2>; 263 assigned-clock-parents = <&k3_clks 38 3>; 264 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 265 ti,timer-pwm; 266 }; 267 268 main_timer3: timer@2430000 { 269 compatible = "ti,am654-timer"; 270 reg = <0x00 0x2430000 0x00 0x400>; 271 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&k3_clks 39 2>; 273 clock-names = "fck"; 274 assigned-clocks = <&k3_clks 39 2>; 275 assigned-clock-parents = <&k3_clks 39 3>; 276 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 277 ti,timer-pwm; 278 }; 279 280 main_timer4: timer@2440000 { 281 compatible = "ti,am654-timer"; 282 reg = <0x00 0x2440000 0x00 0x400>; 283 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&k3_clks 40 2>; 285 clock-names = "fck"; 286 assigned-clocks = <&k3_clks 40 2>; 287 assigned-clock-parents = <&k3_clks 40 3>; 288 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 289 ti,timer-pwm; 290 }; 291 292 main_timer5: timer@2450000 { 293 compatible = "ti,am654-timer"; 294 reg = <0x00 0x2450000 0x00 0x400>; 295 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&k3_clks 41 2>; 297 clock-names = "fck"; 298 assigned-clocks = <&k3_clks 41 2>; 299 assigned-clock-parents = <&k3_clks 41 3>; 300 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 301 ti,timer-pwm; 302 }; 303 304 main_timer6: timer@2460000 { 305 compatible = "ti,am654-timer"; 306 reg = <0x00 0x2460000 0x00 0x400>; 307 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&k3_clks 42 2>; 309 clock-names = "fck"; 310 assigned-clocks = <&k3_clks 42 2>; 311 assigned-clock-parents = <&k3_clks 42 3>; 312 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 313 ti,timer-pwm; 314 }; 315 316 main_timer7: timer@2470000 { 317 compatible = "ti,am654-timer"; 318 reg = <0x00 0x2470000 0x00 0x400>; 319 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&k3_clks 43 2>; 321 clock-names = "fck"; 322 assigned-clocks = <&k3_clks 43 2>; 323 assigned-clock-parents = <&k3_clks 43 3>; 324 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 325 ti,timer-pwm; 326 }; 327 328 main_uart0: serial@2800000 { 329 compatible = "ti,am64-uart", "ti,am654-uart"; 330 reg = <0x00 0x02800000 0x00 0x100>; 331 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 332 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 333 clocks = <&k3_clks 146 0>; 334 clock-names = "fclk"; 335 status = "disabled"; 336 }; 337 338 main_uart1: serial@2810000 { 339 compatible = "ti,am64-uart", "ti,am654-uart"; 340 reg = <0x00 0x02810000 0x00 0x100>; 341 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 342 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 343 clocks = <&k3_clks 152 0>; 344 clock-names = "fclk"; 345 status = "disabled"; 346 }; 347 348 main_uart2: serial@2820000 { 349 compatible = "ti,am64-uart", "ti,am654-uart"; 350 reg = <0x00 0x02820000 0x00 0x100>; 351 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 352 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 353 clocks = <&k3_clks 153 0>; 354 clock-names = "fclk"; 355 status = "disabled"; 356 }; 357 358 main_uart3: serial@2830000 { 359 compatible = "ti,am64-uart", "ti,am654-uart"; 360 reg = <0x00 0x02830000 0x00 0x100>; 361 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 362 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 363 clocks = <&k3_clks 154 0>; 364 clock-names = "fclk"; 365 status = "disabled"; 366 }; 367 368 main_uart4: serial@2840000 { 369 compatible = "ti,am64-uart", "ti,am654-uart"; 370 reg = <0x00 0x02840000 0x00 0x100>; 371 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 372 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 373 clocks = <&k3_clks 155 0>; 374 clock-names = "fclk"; 375 status = "disabled"; 376 }; 377 378 main_uart5: serial@2850000 { 379 compatible = "ti,am64-uart", "ti,am654-uart"; 380 reg = <0x00 0x02850000 0x00 0x100>; 381 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 382 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 383 clocks = <&k3_clks 156 0>; 384 clock-names = "fclk"; 385 status = "disabled"; 386 }; 387 388 main_uart6: serial@2860000 { 389 compatible = "ti,am64-uart", "ti,am654-uart"; 390 reg = <0x00 0x02860000 0x00 0x100>; 391 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 392 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 393 clocks = <&k3_clks 158 0>; 394 clock-names = "fclk"; 395 status = "disabled"; 396 }; 397 398 main_i2c0: i2c@20000000 { 399 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 400 reg = <0x00 0x20000000 0x00 0x100>; 401 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 405 clocks = <&k3_clks 102 2>; 406 clock-names = "fck"; 407 status = "disabled"; 408 }; 409 410 main_i2c1: i2c@20010000 { 411 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 412 reg = <0x00 0x20010000 0x00 0x100>; 413 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 417 clocks = <&k3_clks 103 2>; 418 clock-names = "fck"; 419 status = "disabled"; 420 }; 421 422 main_i2c2: i2c@20020000 { 423 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 424 reg = <0x00 0x20020000 0x00 0x100>; 425 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 429 clocks = <&k3_clks 104 2>; 430 clock-names = "fck"; 431 status = "disabled"; 432 }; 433 434 main_i2c3: i2c@20030000 { 435 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 436 reg = <0x00 0x20030000 0x00 0x100>; 437 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 441 clocks = <&k3_clks 105 2>; 442 clock-names = "fck"; 443 status = "disabled"; 444 }; 445 446 main_spi0: spi@20100000 { 447 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 448 reg = <0x00 0x20100000 0x00 0x400>; 449 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 453 clocks = <&k3_clks 141 0>; 454 status = "disabled"; 455 }; 456 457 main_spi1: spi@20110000 { 458 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 459 reg = <0x00 0x20110000 0x00 0x400>; 460 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 464 clocks = <&k3_clks 142 0>; 465 status = "disabled"; 466 }; 467 468 main_spi2: spi@20120000 { 469 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 470 reg = <0x00 0x20120000 0x00 0x400>; 471 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 475 clocks = <&k3_clks 143 0>; 476 status = "disabled"; 477 }; 478 479 main_gpio_intr: interrupt-controller@a00000 { 480 compatible = "ti,sci-intr"; 481 reg = <0x00 0x00a00000 0x00 0x800>; 482 ti,intr-trigger-type = <1>; 483 interrupt-controller; 484 interrupt-parent = <&gic500>; 485 #interrupt-cells = <1>; 486 ti,sci = <&dmsc>; 487 ti,sci-dev-id = <3>; 488 ti,interrupt-ranges = <0 32 16>; 489 }; 490 491 main_gpio0: gpio@600000 { 492 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 493 reg = <0x0 0x00600000 0x0 0x100>; 494 gpio-controller; 495 #gpio-cells = <2>; 496 interrupt-parent = <&main_gpio_intr>; 497 interrupts = <190>, <191>, <192>, 498 <193>, <194>, <195>; 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 ti,ngpio = <92>; 502 ti,davinci-gpio-unbanked = <0>; 503 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 504 clocks = <&k3_clks 77 0>; 505 clock-names = "gpio"; 506 }; 507 508 main_gpio1: gpio@601000 { 509 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 510 reg = <0x0 0x00601000 0x0 0x100>; 511 gpio-controller; 512 #gpio-cells = <2>; 513 interrupt-parent = <&main_gpio_intr>; 514 interrupts = <180>, <181>, <182>, 515 <183>, <184>, <185>; 516 interrupt-controller; 517 #interrupt-cells = <2>; 518 ti,ngpio = <52>; 519 ti,davinci-gpio-unbanked = <0>; 520 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 521 clocks = <&k3_clks 78 0>; 522 clock-names = "gpio"; 523 }; 524 525 sdhci0: mmc@fa10000 { 526 compatible = "ti,am62-sdhci"; 527 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; 528 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 529 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 530 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; 531 clock-names = "clk_ahb", "clk_xin"; 532 assigned-clocks = <&k3_clks 57 6>; 533 assigned-clock-parents = <&k3_clks 57 8>; 534 mmc-ddr-1_8v; 535 mmc-hs200-1_8v; 536 ti,trm-icp = <0x2>; 537 bus-width = <8>; 538 ti,clkbuf-sel = <0x7>; 539 ti,otap-del-sel-legacy = <0x0>; 540 ti,otap-del-sel-mmc-hs = <0x0>; 541 ti,otap-del-sel-ddr52 = <0x5>; 542 ti,otap-del-sel-hs200 = <0x5>; 543 ti,itap-del-sel-legacy = <0xa>; 544 ti,itap-del-sel-mmc-hs = <0x1>; 545 status = "disabled"; 546 }; 547 548 sdhci1: mmc@fa00000 { 549 compatible = "ti,am62-sdhci"; 550 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; 551 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 552 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 553 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 554 clock-names = "clk_ahb", "clk_xin"; 555 ti,trm-icp = <0x2>; 556 ti,otap-del-sel-legacy = <0x8>; 557 ti,otap-del-sel-sd-hs = <0x0>; 558 ti,otap-del-sel-sdr12 = <0x0>; 559 ti,otap-del-sel-sdr25 = <0x0>; 560 ti,otap-del-sel-sdr50 = <0x8>; 561 ti,otap-del-sel-sdr104 = <0x7>; 562 ti,otap-del-sel-ddr50 = <0x4>; 563 ti,itap-del-sel-legacy = <0xa>; 564 ti,itap-del-sel-sd-hs = <0x1>; 565 ti,itap-del-sel-sdr12 = <0xa>; 566 ti,itap-del-sel-sdr25 = <0x1>; 567 ti,clkbuf-sel = <0x7>; 568 bus-width = <4>; 569 status = "disabled"; 570 }; 571 572 sdhci2: mmc@fa20000 { 573 compatible = "ti,am62-sdhci"; 574 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; 575 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 576 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 577 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 578 clock-names = "clk_ahb", "clk_xin"; 579 ti,trm-icp = <0x2>; 580 ti,otap-del-sel-legacy = <0x8>; 581 ti,otap-del-sel-sd-hs = <0x0>; 582 ti,otap-del-sel-sdr12 = <0x0>; 583 ti,otap-del-sel-sdr25 = <0x0>; 584 ti,otap-del-sel-sdr50 = <0x8>; 585 ti,otap-del-sel-sdr104 = <0x7>; 586 ti,otap-del-sel-ddr50 = <0x8>; 587 ti,itap-del-sel-legacy = <0xa>; 588 ti,itap-del-sel-sd-hs = <0xa>; 589 ti,itap-del-sel-sdr12 = <0xa>; 590 ti,itap-del-sel-sdr25 = <0x1>; 591 ti,clkbuf-sel = <0x7>; 592 status = "disabled"; 593 }; 594 595 usbss0: dwc3-usb@f900000 { 596 compatible = "ti,am62-usb"; 597 reg = <0x00 0x0f900000 0x00 0x800>; 598 clocks = <&k3_clks 161 3>; 599 clock-names = "ref"; 600 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; 601 #address-cells = <2>; 602 #size-cells = <2>; 603 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 604 ranges; 605 status = "disabled"; 606 607 usb0: usb@31000000 { 608 compatible = "snps,dwc3"; 609 reg = <0x00 0x31000000 0x00 0x50000>; 610 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 611 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 612 interrupt-names = "host", "peripheral"; 613 maximum-speed = "high-speed"; 614 dr_mode = "otg"; 615 snps,usb2-gadget-lpm-disable; 616 snps,usb2-lpm-disable; 617 }; 618 }; 619 620 usbss1: dwc3-usb@f910000 { 621 compatible = "ti,am62-usb"; 622 reg = <0x00 0x0f910000 0x00 0x800>; 623 clocks = <&k3_clks 162 3>; 624 clock-names = "ref"; 625 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; 626 #address-cells = <2>; 627 #size-cells = <2>; 628 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 629 ranges; 630 status = "disabled"; 631 632 usb1: usb@31100000 { 633 compatible = "snps,dwc3"; 634 reg = <0x00 0x31100000 0x00 0x50000>; 635 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 636 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 637 interrupt-names = "host", "peripheral"; 638 maximum-speed = "high-speed"; 639 dr_mode = "otg"; 640 snps,usb2-gadget-lpm-disable; 641 snps,usb2-lpm-disable; 642 }; 643 }; 644 645 fss: bus@fc00000 { 646 compatible = "simple-bus"; 647 reg = <0x00 0x0fc00000 0x00 0x70000>; 648 #address-cells = <2>; 649 #size-cells = <2>; 650 ranges; 651 652 ospi0: spi@fc40000 { 653 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 654 reg = <0x00 0x0fc40000 0x00 0x100>, 655 <0x05 0x00000000 0x01 0x00000000>; 656 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 657 cdns,fifo-depth = <256>; 658 cdns,fifo-width = <4>; 659 cdns,trigger-address = <0x0>; 660 clocks = <&k3_clks 75 7>; 661 assigned-clocks = <&k3_clks 75 7>; 662 assigned-clock-parents = <&k3_clks 75 8>; 663 assigned-clock-rates = <166666666>; 664 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 status = "disabled"; 668 }; 669 }; 670 671 cpsw3g: ethernet@8000000 { 672 compatible = "ti,am642-cpsw-nuss"; 673 #address-cells = <2>; 674 #size-cells = <2>; 675 reg = <0x00 0x08000000 0x00 0x200000>; 676 reg-names = "cpsw_nuss"; 677 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; 678 clocks = <&k3_clks 13 0>; 679 assigned-clocks = <&k3_clks 13 3>; 680 assigned-clock-parents = <&k3_clks 13 11>; 681 clock-names = "fck"; 682 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 683 684 dmas = <&main_pktdma 0xc600 15>, 685 <&main_pktdma 0xc601 15>, 686 <&main_pktdma 0xc602 15>, 687 <&main_pktdma 0xc603 15>, 688 <&main_pktdma 0xc604 15>, 689 <&main_pktdma 0xc605 15>, 690 <&main_pktdma 0xc606 15>, 691 <&main_pktdma 0xc607 15>, 692 <&main_pktdma 0x4600 15>; 693 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 694 "tx7", "rx"; 695 696 ethernet-ports { 697 #address-cells = <1>; 698 #size-cells = <0>; 699 700 cpsw_port1: port@1 { 701 reg = <1>; 702 ti,mac-only; 703 label = "port1"; 704 phys = <&phy_gmii_sel 1>; 705 mac-address = [00 00 00 00 00 00]; 706 ti,syscon-efuse = <&wkup_conf 0x200>; 707 }; 708 709 cpsw_port2: port@2 { 710 reg = <2>; 711 ti,mac-only; 712 label = "port2"; 713 phys = <&phy_gmii_sel 2>; 714 mac-address = [00 00 00 00 00 00]; 715 }; 716 }; 717 718 cpsw3g_mdio: mdio@f00 { 719 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 720 reg = <0x00 0xf00 0x00 0x100>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 clocks = <&k3_clks 13 0>; 724 clock-names = "fck"; 725 bus_freq = <1000000>; 726 status = "disabled"; 727 }; 728 729 cpts@3d000 { 730 compatible = "ti,j721e-cpts"; 731 reg = <0x00 0x3d000 0x00 0x400>; 732 clocks = <&k3_clks 13 3>; 733 clock-names = "cpts"; 734 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 735 interrupt-names = "cpts"; 736 ti,cpts-ext-ts-inputs = <4>; 737 ti,cpts-periodic-outputs = <2>; 738 }; 739 }; 740 741 dss: dss@30200000 { 742 compatible = "ti,am625-dss"; 743 reg = <0x00 0x30200000 0x00 0x1000>, /* common */ 744 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ 745 <0x00 0x30206000 0x00 0x1000>, /* vid */ 746 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ 747 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ 748 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ 749 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ 750 <0x00 0x30201000 0x00 0x1000>; /* common1 */ 751 reg-names = "common", "vidl1", "vid", 752 "ovr1", "ovr2", "vp1", "vp2", "common1"; 753 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 754 clocks = <&k3_clks 186 6>, 755 <&dss_vp1_clk>, 756 <&k3_clks 186 2>; 757 clock-names = "fck", "vp1", "vp2"; 758 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 759 status = "disabled"; 760 761 dss_ports: ports { 762 #address-cells = <1>; 763 #size-cells = <0>; 764 }; 765 }; 766 767 hwspinlock: spinlock@2a000000 { 768 compatible = "ti,am64-hwspinlock"; 769 reg = <0x00 0x2a000000 0x00 0x1000>; 770 #hwlock-cells = <1>; 771 }; 772 773 mailbox0_cluster0: mailbox@29000000 { 774 compatible = "ti,am64-mailbox"; 775 reg = <0x00 0x29000000 0x00 0x200>; 776 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 778 #mbox-cells = <1>; 779 ti,mbox-num-users = <4>; 780 ti,mbox-num-fifos = <16>; 781 }; 782 783 ecap0: pwm@23100000 { 784 compatible = "ti,am3352-ecap"; 785 #pwm-cells = <3>; 786 reg = <0x00 0x23100000 0x00 0x100>; 787 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 788 clocks = <&k3_clks 51 0>; 789 clock-names = "fck"; 790 status = "disabled"; 791 }; 792 793 ecap1: pwm@23110000 { 794 compatible = "ti,am3352-ecap"; 795 #pwm-cells = <3>; 796 reg = <0x00 0x23110000 0x00 0x100>; 797 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 798 clocks = <&k3_clks 52 0>; 799 clock-names = "fck"; 800 status = "disabled"; 801 }; 802 803 ecap2: pwm@23120000 { 804 compatible = "ti,am3352-ecap"; 805 #pwm-cells = <3>; 806 reg = <0x00 0x23120000 0x00 0x100>; 807 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 808 clocks = <&k3_clks 53 0>; 809 clock-names = "fck"; 810 status = "disabled"; 811 }; 812 813 main_mcan0: can@20701000 { 814 compatible = "bosch,m_can"; 815 reg = <0x00 0x20701000 0x00 0x200>, 816 <0x00 0x20708000 0x00 0x8000>; 817 reg-names = "m_can", "message_ram"; 818 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 819 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 820 clock-names = "hclk", "cclk"; 821 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 823 interrupt-names = "int0", "int1"; 824 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 825 status = "disabled"; 826 }; 827 828 main_rti0: watchdog@e000000 { 829 compatible = "ti,j7-rti-wdt"; 830 reg = <0x00 0x0e000000 0x00 0x100>; 831 clocks = <&k3_clks 125 0>; 832 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 833 assigned-clocks = <&k3_clks 125 0>; 834 assigned-clock-parents = <&k3_clks 125 2>; 835 }; 836 837 main_rti1: watchdog@e010000 { 838 compatible = "ti,j7-rti-wdt"; 839 reg = <0x00 0x0e010000 0x00 0x100>; 840 clocks = <&k3_clks 126 0>; 841 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 842 assigned-clocks = <&k3_clks 126 0>; 843 assigned-clock-parents = <&k3_clks 126 2>; 844 }; 845 846 main_rti2: watchdog@e020000 { 847 compatible = "ti,j7-rti-wdt"; 848 reg = <0x00 0x0e020000 0x00 0x100>; 849 clocks = <&k3_clks 127 0>; 850 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 851 assigned-clocks = <&k3_clks 127 0>; 852 assigned-clock-parents = <&k3_clks 127 2>; 853 }; 854 855 main_rti3: watchdog@e030000 { 856 compatible = "ti,j7-rti-wdt"; 857 reg = <0x00 0x0e030000 0x00 0x100>; 858 clocks = <&k3_clks 128 0>; 859 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 860 assigned-clocks = <&k3_clks 128 0>; 861 assigned-clock-parents = <&k3_clks 128 2>; 862 }; 863 864 main_rti15: watchdog@e0f0000 { 865 compatible = "ti,j7-rti-wdt"; 866 reg = <0x00 0x0e0f0000 0x00 0x100>; 867 clocks = <&k3_clks 130 0>; 868 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; 869 assigned-clocks = <&k3_clks 130 0>; 870 assigned-clock-parents = <&k3_clks 130 2>; 871 }; 872 873 epwm0: pwm@23000000 { 874 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 875 #pwm-cells = <3>; 876 reg = <0x00 0x23000000 0x00 0x100>; 877 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 878 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 879 clock-names = "tbclk", "fck"; 880 status = "disabled"; 881 }; 882 883 epwm1: pwm@23010000 { 884 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 885 #pwm-cells = <3>; 886 reg = <0x00 0x23010000 0x00 0x100>; 887 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 888 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 889 clock-names = "tbclk", "fck"; 890 status = "disabled"; 891 }; 892 893 epwm2: pwm@23020000 { 894 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 895 #pwm-cells = <3>; 896 reg = <0x00 0x23020000 0x00 0x100>; 897 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 898 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 899 clock-names = "tbclk", "fck"; 900 status = "disabled"; 901 }; 902 903 mcasp0: audio-controller@2b00000 { 904 compatible = "ti,am33xx-mcasp-audio"; 905 reg = <0x00 0x02b00000 0x00 0x2000>, 906 <0x00 0x02b08000 0x00 0x400>; 907 reg-names = "mpu", "dat"; 908 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 910 interrupt-names = "tx", "rx"; 911 912 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 913 dma-names = "tx", "rx"; 914 915 clocks = <&k3_clks 190 0>; 916 clock-names = "fck"; 917 assigned-clocks = <&k3_clks 190 0>; 918 assigned-clock-parents = <&k3_clks 190 2>; 919 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 920 status = "disabled"; 921 }; 922 923 mcasp1: audio-controller@2b10000 { 924 compatible = "ti,am33xx-mcasp-audio"; 925 reg = <0x00 0x02b10000 0x00 0x2000>, 926 <0x00 0x02b18000 0x00 0x400>; 927 reg-names = "mpu", "dat"; 928 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 930 interrupt-names = "tx", "rx"; 931 932 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 933 dma-names = "tx", "rx"; 934 935 clocks = <&k3_clks 191 0>; 936 clock-names = "fck"; 937 assigned-clocks = <&k3_clks 191 0>; 938 assigned-clock-parents = <&k3_clks 191 2>; 939 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 940 status = "disabled"; 941 }; 942 943 mcasp2: audio-controller@2b20000 { 944 compatible = "ti,am33xx-mcasp-audio"; 945 reg = <0x00 0x02b20000 0x00 0x2000>, 946 <0x00 0x02b28000 0x00 0x400>; 947 reg-names = "mpu", "dat"; 948 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 950 interrupt-names = "tx", "rx"; 951 952 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 953 dma-names = "tx", "rx"; 954 955 clocks = <&k3_clks 192 0>; 956 clock-names = "fck"; 957 assigned-clocks = <&k3_clks 192 0>; 958 assigned-clock-parents = <&k3_clks 192 2>; 959 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 960 status = "disabled"; 961 }; 962}; 963