dts/rockchip/rk3036.dtsi

34 		#size-cells = <0>;
40 			reg = <0xf00>;
53 			reg = <0xf01>;
84 		#clock-cells = <0>;
89 		reg = <0x10080000 0x2000>;
92 		ranges = <0 0x10080000 0x2000>;
94 		smp-sram@0 {
96 			reg = <0x00 0x10>;
102 		reg = <0x10090000 0x10000>;
122 		reg = <0x10108000 0x800>;
133 		reg = <0x10108800 0x100>;
138 		#iommu-cells = <0>;
143 		reg = <0x10118000 0x19c>;
155 			#size-cells = <0>;
156 			vop_out_hdmi: endpoint@0 {
157 				reg = <0>;
165 		reg = <0x10118300 0x100>;
170 		#iommu-cells = <0>;
176 		reg = <0x1012d000 0x20>;
181 		reg = <0x1012e000 0x20>;
186 		reg = <0x1012f000 0x20>;
193 		#address-cells = <0>;
195 		reg = <0x10139000 0x1000>,
196 		      <0x1013a000 0x2000>,
197 		      <0x1013c000 0x2000>,
198 		      <0x1013e000 0x2000>;
205 		reg = <0x10180000 0x40000>;
219 		reg = <0x101c0000 0x40000>;
229 		reg = <0x10200000 0x4000>;
248 		reg = <0x10214000 0x4000>;
253 		fifo-depth = <0x100>;
262 		reg = <0x10218000 0x4000>;
267 		fifo-depth = <0x100>;
276 		reg = <0x1021c000 0x4000>;
289 		fifo-depth = <0x100>;
293 		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
301 		reg = <0x10220000 0x4000>;
305 		dmas = <&pdma 0>, <&pdma 1>;
308 		pinctrl-0 = <&i2s_bus>;
309 		#sound-dai-cells = <0>;
316 		reg = <0x10500000 0x4000>;
322 		pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
330 		reg = <0x20000000 0x1000>;
342 		reg = <0x20008000 0x1000>;
348 			#size-cells = <0>;
356 				#power-domain-cells = <0>;
364 				#power-domain-cells = <0>;
371 				#power-domain-cells = <0>;
377 			offset = <0x1d8>;
387 		reg = <0x20030000 0x4000>;
391 		#sound-dai-cells = <0>;
397 		reg = <0x20034000 0x4000>;
402 		pinctrl-0 = <&hdmi_ctl>;
407 			#size-cells = <0>;
409 			hdmi_in: port@0 {
410 				reg = <0>;
425 		reg = <0x20044000 0x20>;
433 		reg = <0x20050000 0x10>;
437 		pinctrl-0 = <&pwm0_pin>;
443 		reg = <0x20050010 0x10>;
447 		pinctrl-0 = <&pwm1_pin>;
453 		reg = <0x20050020 0x10>;
457 		pinctrl-0 = <&pwm2_pin>;
463 		reg = <0x20050030 0x10>;
467 		pinctrl-0 = <&pwm3_pin>;
473 		reg = <0x20056000 0x1000>;
476 		#size-cells = <0>;
480 		pinctrl-0 = <&i2c1_xfer>;
486 		reg = <0x2005a000 0x1000>;
489 		#size-cells = <0>;
493 		pinctrl-0 = <&i2c2_xfer>;
499 		reg = <0x20060000 0x100>;
507 		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
513 		reg = <0x20064000 0x100>;
521 		pinctrl-0 = <&uart1_xfer>;
527 		reg = <0x20068000 0x100>;
535 		pinctrl-0 = <&uart2_xfer>;
541 		reg = <0x20072000 0x1000>;
544 		#size-cells = <0>;
548 		pinctrl-0 = <&i2c0_xfer>;
554 		reg = <0x20074000 0x1000>;
561 		pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
563 		#size-cells = <0>;
569 		reg = <0x20078000 0x4000>;
570 		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
588 			reg = <0x2007c000 0x100>;
601 			reg = <0x20080000 0x100>;
614 			reg = <0x20084000 0x100>;
635 				rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
641 				rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
647 				rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
653 				rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
684 				rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
688 				rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
689 						<0 RK_PB4 1 &pcfg_pull_default>,
690 						<0 RK_PB5 1 &pcfg_pull_default>,
691 						<0 RK_PB6 1 &pcfg_pull_default>;
695 				rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
699 				rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
785 				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
786 						<0 RK_PA1 1 &pcfg_pull_none>;
792 				rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
793 						<0 RK_PA3 1 &pcfg_pull_none>;
826 				rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
827 						<0 RK_PC1 1 &pcfg_pull_none>;
831 				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
835 				rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;