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Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04 |
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| #
5c676780 |
| 21-Dec-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- stratix10 updates
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| #
bd558171 |
| 19-Dec-2018 |
Ang, Chee Hong <chee.hong.ang@intel.com> |
arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration
Select CONFIG_FPGA_STRATIX10 for CONFIG_TARGET_SOCFPGA_STRATIX10.
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
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| #
719afeb0 |
| 17-Aug-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
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| #
934aec71 |
| 30-Jul-2018 |
Marek Vasut <marex@denx.de> |
ARM: socfpga: clk: Obtain handoff base clock via DM
Bind fixed clock driver to the base clock instantiated in the handoff
DT and use DM clock framework to get their clock rate. This replaces
the ad-
ARM: socfpga: clk: Obtain handoff base clock via DM
Bind fixed clock driver to the base clock instantiated in the handoff
DT and use DM clock framework to get their clock rate. This replaces
the ad-hoc DT parsing present thus far.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
show more ...
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| #
d6a61da4 |
| 13-Aug-2018 |
Marek Vasut <marex@denx.de> |
ARM: socfpga: Remove adhoc ethernet reset and configuration
Remove ad-hoc ethernet syscon registers configuration and reset support.
Reset is now handled by the reset framework and the syscon regist
ARM: socfpga: Remove adhoc ethernet reset and configuration
Remove ad-hoc ethernet syscon registers configuration and reset support.
Reset is now handled by the reset framework and the syscon registers are
set in the dwmac_socfpga.c driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
show more ...
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| #
fe88c2fe |
| 13-Aug-2018 |
Marek Vasut <marex@denx.de> |
ARM: socfpga: Enable DM I2C framework on A10
Enable the DM I2C framework on Arria10, so that the DM capable
Designware I2C driver can handle the reset via DM reset framework.
Signed-off-by: Marek V
ARM: socfpga: Enable DM I2C framework on A10
Enable the DM I2C framework on Arria10, so that the DM capable
Designware I2C driver can handle the reset via DM reset framework.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
show more ...
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| #
8145c1c2 |
| 13-Aug-2018 |
Marek Vasut <marex@denx.de> |
ARM: socfpga: Enable DM reset framework on A10
Enable the DM reset framework and DM reset driver on Arria10 both
in U-Boot and in SPL. This lets U-Boot parse reset control from DT.
Signed-off-by: M
ARM: socfpga: Enable DM reset framework on A10
Enable the DM reset framework and DM reset driver on Arria10 both
in U-Boot and in SPL. This lets U-Boot parse reset control from DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
show more ...
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| #
58008cba |
| 23-Jul-2018 |
Michal Simek <michal.simek@xilinx.com> |
Kconfig: Sort bool, default, select and imply options
Another round of sorting Kconfig entries aplhabetically.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@kon
Kconfig: Sort bool, default, select and imply options
Another round of sorting Kconfig entries aplhabetically.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
show more ...
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| #
914bb7ea |
| 13-Jul-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Update SPDX tag in arch/arm/mach-socfpga/spl_a10.c
Signed-off-by: Tom Rini <trini@konsulko.com>
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Revision tags: v2018.07 |
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| #
a684729a |
| 23-May-2018 |
Ley Foon Tan <ley.foon.tan@intel.com> |
arm: socfpga: stratix10: Enable Stratix10 SoC build
Add build support for Stratix SoC
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
arm: socfpga: stratix10: Enable Stratix10 SoC build
Add build support for Stratix SoC
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Conflicts:
arch/arm/Kconfig
arch/arm/mach-socfpga/Kconfig
show more ...
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| #
03b54997 |
| 02-Jul-2018 |
Tom Rini <trini@konsulko.com> |
board/aries: Remove
The various Aries Embedded boards have been orphaned for a year and no
one has come forward to take care of them. Remove.
Signed-off-by: Tom Rini <trini@konsulko.com>
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| #
904e5469 |
| 20-May-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
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Revision tags: v2018.03, v2018.01 |
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| #
901af3e9 |
| 05-Dec-2017 |
Tien Fong Chee <tien.fong.chee@intel.com> |
configs: Add DDR Kconfig support for Arria 10
This patch enables DDR Kconfig support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel
configs: Add DDR Kconfig support for Arria 10
This patch enables DDR Kconfig support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
show more ...
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| #
48befc00 |
| 11-May-2018 |
Marek Vasut <marex@denx.de> |
ARM: socfpga: Clean up Kconfig entries
Shuffle the default Kconfig entries around so it is not such a mess.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin
ARM: socfpga: Clean up Kconfig entries
Shuffle the default Kconfig entries around so it is not such a mess.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
show more ...
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| #
77bba970 |
| 01-Mar-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
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| #
7fb46430 |
| 24-Feb-2018 |
Marek Vasut <marex@denx.de> |
ARM: socfpga: Add new CycloneV SoC Devboards DBM-SoC1 board
Add support for a new boards from devboards.de , the DBM-SoC1 .
This board has one ethernet port, one USB OTG port and USB UART.
Signed-o
ARM: socfpga: Add new CycloneV SoC Devboards DBM-SoC1 board
Add support for a new boards from devboards.de , the DBM-SoC1 .
This board has one ethernet port, one USB OTG port and USB UART.
Signed-off-by: Marek Vasut <marex@denx.de>
show more ...
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Revision tags: v2017.11 |
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| #
0680f1b1 |
| 03-May-2017 |
Ley Foon Tan <ley.foon.tan@intel.com> |
Convert CONFIG_SPL_BOARD_INIT to Kconfig
This converts the following to Kconfig:
CONFIG_SPL_BOARD_INIT
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
[trini: Update the Kconfig logic]
Sign
Convert CONFIG_SPL_BOARD_INIT to Kconfig
This converts the following to Kconfig:
CONFIG_SPL_BOARD_INIT
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
[trini: Update the Kconfig logic]
Signed-off-by: Tom Rini <trini@konsulko.com>
show more ...
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| #
753a4dde |
| 18-May-2017 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
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| #
d89e979c |
| 25-Apr-2017 |
Ley Foon Tan <ley.foon.tan@intel.com> |
arm: socfpga: Enable build for Arria 10
Update Kconfig and Makefile to enable Arria 10.
Clean up Makefile and sorting *.o alphanumerically.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
arm: socfpga: Enable build for Arria 10
Update Kconfig and Makefile to enable Arria 10.
Clean up Makefile and sorting *.o alphanumerically.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
show more ...
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| #
4f66e09b |
| 09-May-2017 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
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| #
9ad99bee |
| 25-Apr-2017 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
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| #
6bd041f0 |
| 18-Apr-2017 |
Dalon Westergreen <dwesterg@gmail.com> |
arm: socfpga: add cyclone5 based de10-nano board
Add support for the Terasic DE10-Nano board. The board
is based on the DE0-Nano-Soc board but adds a larger FPGA
and an HDMI output.
Signed-off-by:
arm: socfpga: add cyclone5 based de10-nano board
Add support for the Terasic DE10-Nano board. The board
is based on the DE0-Nano-Soc board but adds a larger FPGA
and an HDMI output.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
show more ...
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| #
c1a16c3a |
| 14-Apr-2017 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
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| #
707cd012 |
| 05-Apr-2017 |
Ley Foon Tan <ley.foon.tan@intel.com> |
arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig
Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have differe
arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig
Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
show more ...
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| #
a548bc51 |
| 05-Apr-2017 |
Marek Vasut <marex@denx.de> |
ARM: socfpga: Rename MCVEVK
The board is now manufactured by Aries Embedded GmbH , rename it.
Signed-off-by: Marek Vasut <marex@denx.de>
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