1if ARCH_SOCFPGA 2 3config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE 4 default 0xa2 5 6config TARGET_SOCFPGA_ARRIA5 7 bool 8 select TARGET_SOCFPGA_GEN5 9 10config TARGET_SOCFPGA_ARRIA10 11 bool 12 select SPL_BOARD_INIT if SPL 13 14config TARGET_SOCFPGA_CYCLONE5 15 bool 16 select TARGET_SOCFPGA_GEN5 17 18config TARGET_SOCFPGA_GEN5 19 bool 20 select ALTERA_SDRAM 21 22choice 23 prompt "Altera SOCFPGA board select" 24 optional 25 26config TARGET_SOCFPGA_ARRIA10_SOCDK 27 bool "Altera SOCFPGA SoCDK (Arria 10)" 28 select TARGET_SOCFPGA_ARRIA10 29 30config TARGET_SOCFPGA_ARRIA5_SOCDK 31 bool "Altera SOCFPGA SoCDK (Arria V)" 32 select TARGET_SOCFPGA_ARRIA5 33 34config TARGET_SOCFPGA_CYCLONE5_SOCDK 35 bool "Altera SOCFPGA SoCDK (Cyclone V)" 36 select TARGET_SOCFPGA_CYCLONE5 37 38config TARGET_SOCFPGA_ARIES_MCVEVK 39 bool "Aries MCVEVK (Cyclone V)" 40 select TARGET_SOCFPGA_CYCLONE5 41 42config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 43 bool "Devboards DBM-SoC1 (Cyclone V)" 44 select TARGET_SOCFPGA_CYCLONE5 45 46config TARGET_SOCFPGA_EBV_SOCRATES 47 bool "EBV SoCrates (Cyclone V)" 48 select TARGET_SOCFPGA_CYCLONE5 49 50config TARGET_SOCFPGA_IS1 51 bool "IS1 (Cyclone V)" 52 select TARGET_SOCFPGA_CYCLONE5 53 54config TARGET_SOCFPGA_SAMTEC_VINING_FPGA 55 bool "samtec VIN|ING FPGA (Cyclone V)" 56 select BOARD_LATE_INIT 57 select TARGET_SOCFPGA_CYCLONE5 58 59config TARGET_SOCFPGA_SR1500 60 bool "SR1500 (Cyclone V)" 61 select TARGET_SOCFPGA_CYCLONE5 62 63config TARGET_SOCFPGA_TERASIC_DE0_NANO 64 bool "Terasic DE0-Nano-Atlas (Cyclone V)" 65 select TARGET_SOCFPGA_CYCLONE5 66 67config TARGET_SOCFPGA_TERASIC_DE10_NANO 68 bool "Terasic DE10-Nano (Cyclone V)" 69 select TARGET_SOCFPGA_CYCLONE5 70 71config TARGET_SOCFPGA_TERASIC_DE1_SOC 72 bool "Terasic DE1-SoC (Cyclone V)" 73 select TARGET_SOCFPGA_CYCLONE5 74 75config TARGET_SOCFPGA_TERASIC_SOCKIT 76 bool "Terasic SoCkit (Cyclone V)" 77 select TARGET_SOCFPGA_CYCLONE5 78 79endchoice 80 81config SYS_BOARD 82 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 83 default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 84 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 85 default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 86 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 87 default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 88 default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 89 default "is1" if TARGET_SOCFPGA_IS1 90 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK 91 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 92 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES 93 default "sr1500" if TARGET_SOCFPGA_SR1500 94 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 95 96config SYS_VENDOR 97 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK 98 default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK 99 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK 100 default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK 101 default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 102 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES 103 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 104 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO 105 default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC 106 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO 107 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT 108 109config SYS_SOC 110 default "socfpga" 111 112config SYS_CONFIG_NAME 113 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 114 default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 115 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 116 default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 117 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 118 default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 119 default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 120 default "socfpga_is1" if TARGET_SOCFPGA_IS1 121 default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK 122 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 123 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES 124 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 125 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 126 127endif 128