xref: /openbmc/u-boot/arch/arm/mach-socfpga/Kconfig (revision fe88c2fea7e1081993dbb4207f6610eb5d8ae912)
1if ARCH_SOCFPGA
2
3config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
4	default 0xa2
5
6config TARGET_SOCFPGA_ARRIA5
7	bool
8	select TARGET_SOCFPGA_GEN5
9
10config TARGET_SOCFPGA_ARRIA10
11	bool
12	select ALTERA_SDRAM
13	select SPL_BOARD_INIT if SPL
14	select DM_I2C
15	select DM_RESET
16	select SPL_DM_RESET if SPL
17
18config TARGET_SOCFPGA_CYCLONE5
19	bool
20	select TARGET_SOCFPGA_GEN5
21
22config TARGET_SOCFPGA_GEN5
23	bool
24	select ALTERA_SDRAM
25
26config TARGET_SOCFPGA_STRATIX10
27	bool
28	select ARMV8_MULTIENTRY
29	select ARMV8_SET_SMPEN
30	select ARMV8_SPIN_TABLE
31
32choice
33	prompt "Altera SOCFPGA board select"
34	optional
35
36config TARGET_SOCFPGA_ARRIA10_SOCDK
37	bool "Altera SOCFPGA SoCDK (Arria 10)"
38	select TARGET_SOCFPGA_ARRIA10
39
40config TARGET_SOCFPGA_ARRIA5_SOCDK
41	bool "Altera SOCFPGA SoCDK (Arria V)"
42	select TARGET_SOCFPGA_ARRIA5
43
44config TARGET_SOCFPGA_CYCLONE5_SOCDK
45	bool "Altera SOCFPGA SoCDK (Cyclone V)"
46	select TARGET_SOCFPGA_CYCLONE5
47
48config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
49	bool "Devboards DBM-SoC1 (Cyclone V)"
50	select TARGET_SOCFPGA_CYCLONE5
51
52config TARGET_SOCFPGA_EBV_SOCRATES
53	bool "EBV SoCrates (Cyclone V)"
54	select TARGET_SOCFPGA_CYCLONE5
55
56config TARGET_SOCFPGA_IS1
57	bool "IS1 (Cyclone V)"
58	select TARGET_SOCFPGA_CYCLONE5
59
60config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
61	bool "samtec VIN|ING FPGA (Cyclone V)"
62	select BOARD_LATE_INIT
63	select TARGET_SOCFPGA_CYCLONE5
64
65config TARGET_SOCFPGA_SR1500
66	bool "SR1500 (Cyclone V)"
67	select TARGET_SOCFPGA_CYCLONE5
68
69config TARGET_SOCFPGA_STRATIX10_SOCDK
70	bool "Intel SOCFPGA SoCDK (Stratix 10)"
71	select TARGET_SOCFPGA_STRATIX10
72
73config TARGET_SOCFPGA_TERASIC_DE0_NANO
74	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
75	select TARGET_SOCFPGA_CYCLONE5
76
77config TARGET_SOCFPGA_TERASIC_DE10_NANO
78	bool "Terasic DE10-Nano (Cyclone V)"
79	select TARGET_SOCFPGA_CYCLONE5
80
81config TARGET_SOCFPGA_TERASIC_DE1_SOC
82	bool "Terasic DE1-SoC (Cyclone V)"
83	select TARGET_SOCFPGA_CYCLONE5
84
85config TARGET_SOCFPGA_TERASIC_SOCKIT
86	bool "Terasic SoCkit (Cyclone V)"
87	select TARGET_SOCFPGA_CYCLONE5
88
89endchoice
90
91config SYS_BOARD
92	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
93	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
94	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
95	default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
96	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
97	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
98	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
99	default "is1" if TARGET_SOCFPGA_IS1
100	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
101	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
102	default "sr1500" if TARGET_SOCFPGA_SR1500
103	default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
104	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
105
106config SYS_VENDOR
107	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
108	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
109	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
110	default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
111	default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
112	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
113	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
114	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
115	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
116	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
117	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
118
119config SYS_SOC
120	default "socfpga"
121
122config SYS_CONFIG_NAME
123	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
124	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
125	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
126	default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
127	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
128	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
129	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
130	default "socfpga_is1" if TARGET_SOCFPGA_IS1
131	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
132	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
133	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
134	default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
135	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
136
137endif
138