Searched refs:pcw (Results 1 – 7 of 7) sorted by relevance
| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-pll.c | 41 u32 pcw, int postdiv) in __mtk_pll_recalc_rate() argument
54 vco = (u64)fin * pcw; in __mtk_pll_recalc_rate()
115 val |= pcw << pll->data->pcw_shift; in mtk_pll_set_rate_regs()
171 *pcw = (u32)_pcw; in mtk_pll_calc_values()
178 u32 pcw = 0; in mtk_pll_set_rate() local
182 mtk_pll_set_rate_regs(pll, pcw, postdiv); in mtk_pll_set_rate()
191 u32 pcw; in mtk_pll_recalc_rate() local
196 pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift; in mtk_pll_recalc_rate()
197 pcw &= GENMASK(pll->data->pcwbits - 1, 0); in mtk_pll_recalc_rate()
206 u32 pcw = 0; in mtk_pll_round_rate() local
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| H A D | clk-pllfh.c | 32 u32 pcw = 0; in mtk_fhctl_set_rate() local
35 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_fhctl_set_rate()
37 return fh->ops->hopping(fh, pcw, postdiv); in mtk_fhctl_set_rate()
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| H A D | clk-pll.h | 94 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mtk.c | 83 u32 fin, u32 pcw, int postdiv) in __mtk_pll_recalc_rate() argument
93 vco = (u64)fin * pcw; in __mtk_pll_recalc_rate()
131 val |= pcw << pll->pcw_shift; in mtk_pll_set_rate_regs()
170 *pcw = (u32)_pcw; in mtk_pll_calc_values()
175 u32 pcw = 0; in mtk_apmixedsys_set_rate() local
178 mtk_pll_calc_values(clk, &pcw, &postdiv, rate); in mtk_apmixedsys_set_rate()
179 mtk_pll_set_rate_regs(clk, pcw, postdiv); in mtk_apmixedsys_set_rate()
189 u32 pcw; in mtk_apmixedsys_get_rate() local
195 pcw = readl(priv->base + pll->pcw_reg) >> pll->pcw_shift; in mtk_apmixedsys_get_rate()
196 pcw &= GENMASK(pll->pcwbits - 1, 0); in mtk_apmixedsys_get_rate()
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| /openbmc/linux/drivers/phy/mediatek/ |
| H A D | phy-mtk-mipi-dsi-mt8183.c | 52 u64 pcw; in mtk_mipi_tx_pll_enable() local
81 pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 26000000); in mtk_mipi_tx_pll_enable()
82 writel(pcw, base + MIPITX_PLL_CON0); in mtk_mipi_tx_pll_enable()
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| H A D | phy-mtk-hdmi-mt8195.c | 213 u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw; in mtk_hdmi_pll_calc() local
273 pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH, in mtk_hdmi_pll_calc()
276 if (pcw > GENMASK_ULL(32, 0)) in mtk_hdmi_pll_calc()
279 fbkdiv_high = FIELD_GET(GENMASK_ULL(63, 32), pcw); in mtk_hdmi_pll_calc()
280 fbkdiv_low = FIELD_GET(GENMASK(31, 0), pcw); in mtk_hdmi_pll_calc()
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| H A D | phy-mtk-mipi-dsi-mt8173.c | 127 u64 pcw; in mtk_mipi_tx_pll_prepare() local
196 pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24, 26000000); in mtk_mipi_tx_pll_prepare()
197 writel(pcw, base + MIPITX_DSI_PLL_CON2); in mtk_mipi_tx_pll_prepare()
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