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Searched refs:UVD_VCPU_CNTL__TRCE_MUX_MASK (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h790 #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L macro
H A Duvd_4_2_sh_mask.h551 #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 macro
H A Duvd_3_1_sh_mask.h547 #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 macro
H A Duvd_6_0_sh_mask.h585 #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 macro
H A Duvd_5_0_sh_mask.h583 #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_sh_mask.h2761 #define UVD_VCPU_CNTL__TRCE_MUX_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2761 #define UVD_VCPU_CNTL__TRCE_MUX_MASK … macro
H A Dvcn_2_6_0_sh_mask.h114 #define UVD_VCPU_CNTL__TRCE_MUX_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3820 #define UVD_VCPU_CNTL__TRCE_MUX_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4068 #define UVD_VCPU_CNTL__TRCE_MUX_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4106 #define UVD_VCPU_CNTL__TRCE_MUX_MASK … macro