Searched refs:SDMA_PKT_POLL_REGMEM_DW5_INTERVAL (Results 1 – 12 of 12) sorted by relevance
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | sdma_v2_4.c | 291 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_hdp_flush() 777 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_pipeline_sync() 804 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_vm_flush()
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H A D | sdma_v3_0.c | 465 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_hdp_flush() 1048 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_pipeline_sync() 1075 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_vm_flush()
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H A D | sdma_v6_0.c | 323 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v6_0_ring_emit_hdp_flush() 1168 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v6_0_ring_emit_pipeline_sync() 1228 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v6_0_ring_emit_reg_wait()
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H A D | sdma_v5_2.c | 316 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v5_2_ring_emit_hdp_flush() 1131 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v5_2_ring_emit_pipeline_sync() 1171 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v5_2_ring_emit_reg_wait()
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H A D | sdma_v5_0.c | 500 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v5_0_ring_emit_hdp_flush() 1283 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v5_0_ring_emit_pipeline_sync() 1323 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v5_0_ring_emit_reg_wait()
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H A D | tonga_sdma_pkt_open.h | 2019 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
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H A D | iceland_sdma_pkt_open.h | 2019 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
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H A D | sdma_v4_4_2.c | 352 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ in sdma_v4_4_2_wait_reg_mem()
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H A D | vega10_sdma_pkt_open.h | 2511 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
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H A D | sdma_v4_0.c | 801 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ in sdma_v4_0_wait_reg_mem()
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H A D | navi10_sdma_pkt_open.h | 3835 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
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H A D | sdma_v6_0_0_pkt_open.h | 4539 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
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