/openbmc/u-boot/doc/device-tree-bindings/clock/ |
H A D | st,stm32-rcc.txt | 4 The RCC IP is both a reset and a clock controller. 35 The secondary index is the bit number within the RCC register bank, starting 36 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). 42 drivers of the RCC IP, macros are available to generate the index in 84 The index is the bit number within the RCC registers bank, starting from RCC
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H A D | st,stm32mp1.txt | 5 for RCC IP and on fixed clocks. 8 RCC CLOCK = st,stm32mp1-rcc-clk 11 The RCC IP is both a reset and a clock controller but this documentation only 27 with value equals to RCC clock specifier as defined in 34 with DIV coding defined in RCC associated register RCC_xxxDIVR 61 with DIV value as defined in RCC spec: 204 in device tree clk-hsi is the clock after HSIDIV (ck_hsi in RCC doc)
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H A D | st,stm32h7-rcc.txt | 4 The RCC IP is both a reset and a clock controller. 137 The index is the bit number within the RCC registers bank, starting from RCC
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | st,stm32-rcc.txt | 4 The RCC IP is both a reset and a clock controller. 42 The secondary index is the bit number within the RCC register bank, starting 43 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). 49 drivers of the RCC IP, macros are available to generate the index in 127 The index is the bit number within the RCC registers bank, starting from RCC
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H A D | st,stm32mp1-rcc.yaml | 13 The RCC IP is both a reset and a clock controller. 14 RCC makes also power management (resume/supend and wakeup interrupt). 33 The index is the bit number within the RCC registers bank, starting from RCC
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H A D | st,stm32h7-rcc.txt | 4 The RCC IP is both a reset and a clock controller. 59 The index is the bit number within the RCC registers bank, starting from RCC
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/openbmc/qemu/tests/qtest/ |
H A D | cmsdk-apb-watchdog-test.c | 36 #define RCC 0x60 macro 90 rcc = readl(SSYS_BASE + RCC); in test_clock_change() 93 writel(SSYS_BASE + RCC, rcc); in test_clock_change()
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/openbmc/linux/Documentation/devicetree/bindings/reset/ |
H A D | st,stm32-rcc.txt | 4 The RCC IP is both a reset and a clock controller.
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H A D | st,stm32mp1-rcc.txt | 4 The RCC IP is both a reset and a clock controller.
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/openbmc/u-boot/doc/device-tree-bindings/reset/ |
H A D | st,stm32-rcc.txt | 4 The RCC IP is both a reset and a clock controller.
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/openbmc/u-boot/drivers/clk/ |
H A D | Kconfig | 54 This clock driver adds support for RCC clock management 94 bool "Enable RCC clock driver for STM32MP1" 98 Enable the STM32 clock (RCC) driver. Enable support for
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/openbmc/qemu/hw/misc/ |
H A D | trace-events | 182 stm32l4x5_rcc_read(uint64_t addr, uint32_t data) "RCC: Read <0x%" PRIx64 "> -> 0x%" PRIx32 183 stm32l4x5_rcc_write(uint64_t addr, uint32_t data) "RCC: Write <0x%" PRIx64 "> <- 0x%" PRIx32 184 stm32l4x5_rcc_mux_enable(uint32_t mux_id) "RCC: Mux %d enabled" 185 stm32l4x5_rcc_mux_disable(uint32_t mux_id) "RCC: Mux %d disabled" 186 …ier, uint32_t new_multiplier, uint32_t old_divider, uint32_t new_divider) "RCC: Mux %d factor chan… 187 stm32l4x5_rcc_mux_set_src(uint32_t mux_id, uint32_t old_src, uint32_t new_src) "RCC: Mux %d source … 188 …, uint32_t src, uint64_t src_freq, uint32_t multiplier, uint32_t divider) "RCC: Mux %d src %d upda… 189 …iplier(uint32_t pll_id, uint32_t old_multiplier, uint32_t new_multiplier) "RCC: PLL %u: vco_multip… 190 stm32l4x5_rcc_pll_channel_enable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u ena… 191 stm32l4x5_rcc_pll_channel_disable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u di… [all …]
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/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | stm32-dwmac.yaml | 87 set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125. 93 select RCC clock instead of ETH_REF_CLK.
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/openbmc/qemu/docs/system/arm/ |
H A D | b-l475e-iot01a.rst | 20 - STM32L4x5 RCC (Reset and clock control)
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H A D | stm32.rst | 56 * Reset and Clock Controller (RCC)
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/openbmc/u-boot/drivers/misc/ |
H A D | Kconfig | 203 bool "Enable RCC driver for the STM32 SoC's family" 206 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
H A D | st,stm32-rproc.yaml | 49 Reference to the system configuration which holds the RCC trust zone mode
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/openbmc/linux/drivers/reset/ |
H A D | Kconfig | 228 - RCC reset controller in STM32 MCUs
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/openbmc/qemu/hw/net/ |
H A D | pcnet.c | 294 GET_FIELD((R)->msg_length, RMDM, RCC), \
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