1d0fb9657SStefano Garzarella# See docs/devel/tracing.rst for syntax documentation. 26b5bacf6SDaniel P. Berrange 3d26af5deSNiek Linnenbank# allwinner-cpucfg.c 42539eadeSPhilippe Mathieu-Daudéallwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIx32 5d26af5deSNiek Linnenbankallwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 6d26af5deSNiek Linnenbankallwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 7d26af5deSNiek Linnenbank 8b71d0385SNiek Linnenbank# allwinner-h3-dramc.c 9b71d0385SNiek Linnenbankallwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror" 10b71d0385SNiek Linnenbankallwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64 11b71d0385SNiek Linnenbankallwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 12b71d0385SNiek Linnenbankallwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 13b71d0385SNiek Linnenbankallwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 14b71d0385SNiek Linnenbankallwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 15b71d0385SNiek Linnenbankallwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 16b71d0385SNiek Linnenbankallwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 17b71d0385SNiek Linnenbank 184a52ef61Sqianfan Zhao# allwinner-r40-dramc.c 194a52ef61Sqianfan Zhaoallwinner_r40_dramc_detect_cells_disable(void) "Disable detect cells" 204a52ef61Sqianfan Zhaoallwinner_r40_dramc_detect_cells_enable(void) "Enable detect cells" 214a52ef61Sqianfan Zhaoallwinner_r40_dramc_map_rows(uint8_t row_bits, uint8_t bank_bits, uint8_t col_bits) "DRAM layout: row_bits %d, bank_bits %d, col_bits %d" 224a52ef61Sqianfan Zhaoallwinner_r40_dramc_offset_to_cell(uint64_t offset, int row, int bank, int col) "offset 0x%" PRIx64 " row %d bank %d col %d" 234a52ef61Sqianfan Zhaoallwinner_r40_dramc_detect_cell_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 "" 244a52ef61Sqianfan Zhaoallwinner_r40_dramc_detect_cell_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 "" 254a52ef61Sqianfan Zhaoallwinner_r40_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 264a52ef61Sqianfan Zhaoallwinner_r40_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 274a52ef61Sqianfan Zhaoallwinner_r40_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 284a52ef61Sqianfan Zhaoallwinner_r40_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 294a52ef61Sqianfan Zhaoallwinner_r40_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 304a52ef61Sqianfan Zhaoallwinner_r40_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 314a52ef61Sqianfan Zhao 326556617cSNiek Linnenbank# allwinner-sid.c 336556617cSNiek Linnenbankallwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 346556617cSNiek Linnenbankallwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 356556617cSNiek Linnenbank 3605def917Sqianfan Zhao# allwinner-sramc.c 3705def917Sqianfan Zhaoallwinner_sramc_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 3805def917Sqianfan Zhaoallwinner_sramc_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 3905def917Sqianfan Zhao 40dc288de0SMichael Rolnik# avr_power.c 41dc288de0SMichael Rolnikavr_power_read(uint8_t value) "power_reduc read value:%u" 42dc288de0SMichael Rolnikavr_power_write(uint8_t value) "power_reduc write value:%u" 43dc288de0SMichael Rolnik 44a9545430Sqianfan Zhao# axp2xx 45a9545430Sqianfan Zhaoaxp2xx_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8 46a9545430Sqianfan Zhaoaxp2xx_select(uint8_t reg) "Accessing reg 0x%" PRIx8 47a9545430Sqianfan Zhaoaxp2xx_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8 48632dfea3SStrahinja Jankovic 49500016e5SMarkus Armbruster# eccmemctl.c 508908eb1aSVladimir Sementsov-Ogievskiyecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" 518908eb1aSVladimir Sementsov-Ogievskiyecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" 528908eb1aSVladimir Sementsov-Ogievskiyecc_mem_writel_mfsr(uint32_t val) "Write memory fault status 0x%08x" 538908eb1aSVladimir Sementsov-Ogievskiyecc_mem_writel_vcr(uint32_t val) "Write slot configuration 0x%08x" 548908eb1aSVladimir Sementsov-Ogievskiyecc_mem_writel_dr(uint32_t val) "Write diagnostic 0x%08x" 558908eb1aSVladimir Sementsov-Ogievskiyecc_mem_writel_ecr0(uint32_t val) "Write event count 1 0x%08x" 568908eb1aSVladimir Sementsov-Ogievskiyecc_mem_writel_ecr1(uint32_t val) "Write event count 2 0x%08x" 578908eb1aSVladimir Sementsov-Ogievskiyecc_mem_readl_mer(uint32_t ret) "Read memory enable 0x%08x" 588908eb1aSVladimir Sementsov-Ogievskiyecc_mem_readl_mdr(uint32_t ret) "Read memory delay 0x%08x" 598908eb1aSVladimir Sementsov-Ogievskiyecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status 0x%08x" 608908eb1aSVladimir Sementsov-Ogievskiyecc_mem_readl_vcr(uint32_t ret) "Read slot configuration 0x%08x" 618908eb1aSVladimir Sementsov-Ogievskiyecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 0x%08x" 628908eb1aSVladimir Sementsov-Ogievskiyecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 0x%08x" 638908eb1aSVladimir Sementsov-Ogievskiyecc_mem_readl_dr(uint32_t ret) "Read diagnostic 0x%08x" 648908eb1aSVladimir Sementsov-Ogievskiyecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 0x%08x" 658908eb1aSVladimir Sementsov-Ogievskiyecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 0x%08x" 668908eb1aSVladimir Sementsov-Ogievskiyecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = 0x%02x" 678908eb1aSVladimir Sementsov-Ogievskiyecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= 0x%02x" 686b5bacf6SDaniel P. Berrange 696007523aSPhilippe Mathieu-Daudé# empty_slot.c 706007523aSPhilippe Mathieu-Daudéempty_slot_write(uint64_t addr, unsigned width, uint64_t value, unsigned size, const char *name) "wr addr:0x%04"PRIx64" data:0x%0*"PRIx64" size %u [%s]" 716007523aSPhilippe Mathieu-Daudé 72500016e5SMarkus Armbruster# slavio_misc.c 736b5bacf6SDaniel P. Berrangeslavio_misc_update_irq_raise(void) "Raise IRQ" 746b5bacf6SDaniel P. Berrangeslavio_misc_update_irq_lower(void) "Lower IRQ" 756b5bacf6SDaniel P. Berrangeslavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d" 768908eb1aSVladimir Sementsov-Ogievskiyslavio_cfg_mem_writeb(uint32_t val) "Write config 0x%02x" 778908eb1aSVladimir Sementsov-Ogievskiyslavio_cfg_mem_readb(uint32_t ret) "Read config 0x%02x" 788908eb1aSVladimir Sementsov-Ogievskiyslavio_diag_mem_writeb(uint32_t val) "Write diag 0x%02x" 798908eb1aSVladimir Sementsov-Ogievskiyslavio_diag_mem_readb(uint32_t ret) "Read diag 0x%02x" 808908eb1aSVladimir Sementsov-Ogievskiyslavio_mdm_mem_writeb(uint32_t val) "Write modem control 0x%02x" 818908eb1aSVladimir Sementsov-Ogievskiyslavio_mdm_mem_readb(uint32_t ret) "Read modem control 0x%02x" 828908eb1aSVladimir Sementsov-Ogievskiyslavio_aux1_mem_writeb(uint32_t val) "Write aux1 0x%02x" 838908eb1aSVladimir Sementsov-Ogievskiyslavio_aux1_mem_readb(uint32_t ret) "Read aux1 0x%02x" 848908eb1aSVladimir Sementsov-Ogievskiyslavio_aux2_mem_writeb(uint32_t val) "Write aux2 0x%02x" 858908eb1aSVladimir Sementsov-Ogievskiyslavio_aux2_mem_readb(uint32_t ret) "Read aux2 0x%02x" 868908eb1aSVladimir Sementsov-Ogievskiyapc_mem_writeb(uint32_t val) "Write power management 0x%02x" 878908eb1aSVladimir Sementsov-Ogievskiyapc_mem_readb(uint32_t ret) "Read power management 0x%02x" 888908eb1aSVladimir Sementsov-Ogievskiyslavio_sysctrl_mem_writel(uint32_t val) "Write system control 0x%08x" 898908eb1aSVladimir Sementsov-Ogievskiyslavio_sysctrl_mem_readl(uint32_t ret) "Read system control 0x%08x" 908908eb1aSVladimir Sementsov-Ogievskiyslavio_led_mem_writew(uint32_t val) "Write diagnostic LED 0x%04x" 918908eb1aSVladimir Sementsov-Ogievskiyslavio_led_mem_readw(uint32_t ret) "Read diagnostic LED 0x%04x" 926b5bacf6SDaniel P. Berrange 93500016e5SMarkus Armbruster# aspeed_scu.c 941c8a2388SAndrew Jefferyaspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 95673a6d16SCédric Le Goateraspeed_scu_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 96*e7c8106dSJamin Linaspeed_ast2700_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 97*e7c8106dSJamin Linaspeed_ast2700_scu_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 98*e7c8106dSJamin Linaspeed_ast2700_scuio_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 99*e7c8106dSJamin Linaspeed_ast2700_scuio_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 100dd73185bSPeter Maydell 101dec97760SMarkus Armbruster# mps2-scc.c 102dd73185bSPeter Maydellmps2_scc_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 103dd73185bSPeter Maydellmps2_scc_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 104dd73185bSPeter Maydellmps2_scc_reset(void) "MPS2 SCC: reset" 105dd73185bSPeter Maydellmps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32 106dd73185bSPeter Maydellmps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32 1070ee1e1f4SSubbaraya Sundeep 108dec97760SMarkus Armbruster# mps2-fpgaio.c 1099a52d999SPeter Maydellmps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 1109a52d999SPeter Maydellmps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 1119a52d999SPeter Maydellmps2_fpgaio_reset(void) "MPS2 FPGAIO: reset" 1129a52d999SPeter Maydell 113500016e5SMarkus Armbruster# msf2-sysreg.c 114787bbc30SDaniel P. Berrangémsf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" PRIx64 " data 0x%" PRIx32 " prev 0x%" PRIx32 115787bbc30SDaniel P. Berrangémsf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" PRIx64 " data 0x%08" PRIx32 1160ee1e1f4SSubbaraya Sundeepmsf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register" 11730b2f870SAndrey Smirnov 118500016e5SMarkus Armbruster# imx7_gpr.c 119787bbc30SDaniel P. Berrangéimx7_gpr_read(uint64_t offset) "addr 0x%08" PRIx64 120787bbc30SDaniel P. Berrangéimx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx64 12151f233ecSMark Cave-Ayland 122bb2fc5b9SBernhard Beschow# imx7_snvs.c 1236f9c3aaaSNikita Ostrenkovimx7_snvs_read(uint64_t offset, uint64_t value, unsigned size) "i.MX SNVS read: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" 1246f9c3aaaSNikita Ostrenkovimx7_snvs_write(uint64_t offset, uint64_t value, unsigned size) "i.MX SNVS write: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" 125bb2fc5b9SBernhard Beschow 126500016e5SMarkus Armbruster# mos6522.c 12751f233ecSMark Cave-Aylandmos6522_set_counter(int index, unsigned int val) "T%d.counter=%d" 1282539eadeSPhilippe Mathieu-Daudémos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d counter=0x%"PRIx64 " delta_next=0x%"PRIx64 12951f233ecSMark Cave-Aylandmos6522_set_sr_int(void) "set sr_int" 1306c726698SMark Cave-Aylandmos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64 1316c726698SMark Cave-Aylandmos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%s] val=0x%x" 1329eb8040cSPeter Maydell 133e331f79eSHavard Skinnemoen# npcm7xx_clk.c 134e331f79eSHavard Skinnemoennpcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 135e331f79eSHavard Skinnemoennpcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 136e331f79eSHavard Skinnemoen 137e5a7ba87SHavard Skinnemoen# npcm7xx_gcr.c 138e5a7ba87SHavard Skinnemoennpcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 139e5a7ba87SHavard Skinnemoennpcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 140e5a7ba87SHavard Skinnemoen 141380a37e4SHao Wu# npcm7xx_mft.c 142380a37e4SHao Wunpcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 143380a37e4SHao Wunpcm7xx_mft_write(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 144380a37e4SHao Wunpcm7xx_mft_rpm(const char *clock, uint32_t clock_hz, int state, int32_t cnt, uint32_t rpm, uint32_t duty) " fan clk: %s clock_hz: %" PRIu32 ", state: %d, cnt: %" PRIi32 ", rpm: %" PRIu32 ", duty: %" PRIu32 145380a37e4SHao Wunpcm7xx_mft_capture(const char *name, int irq_level) "%s: level: %d" 146380a37e4SHao Wunpcm7xx_mft_update_clock(const char *name, uint16_t sel, uint64_t clock_period, uint64_t prescaled_clock_period) "%s: sel: 0x%02" PRIx16 ", period: %" PRIu64 ", prescaled: %" PRIu64 147380a37e4SHao Wunpcm7xx_mft_set_duty(const char *name, int n, int value) "%s[%d]: %d" 148380a37e4SHao Wu 149326ccfe2SHavard Skinnemoen# npcm7xx_rng.c 150326ccfe2SHavard Skinnemoennpcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" 151326ccfe2SHavard Skinnemoennpcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" 152326ccfe2SHavard Skinnemoen 1531e943c58SHao Wu# npcm7xx_pwm.c 1541e943c58SHao Wunpcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 1551e943c58SHao Wunpcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 1561e943c58SHao Wunpcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u" 1571e943c58SHao Wunpcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u" 1581e943c58SHao Wu 159b15e402fSMarkus Armbruster# stm32f4xx_syscfg.c 160cba42d61SMichael Tokarevstm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interrupt: GPIO: %d, Line: %d; Level: %d" 161870c034dSAlistair Francisstm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" 162870c034dSAlistair Francisstm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " 163870c034dSAlistair Francisstm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" 164870c034dSAlistair Francis 165b15e402fSMarkus Armbruster# stm32f4xx_exti.c 1669b4b4e51SMichael Tokarevstm32f4xx_exti_set_irq(int irq, int level) "Set EXTI: %d to %d" 167e64d8c83SAlistair Francisstm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " 168e64d8c83SAlistair Francisstm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" 169e64d8c83SAlistair Francis 17020936684SInès Varhol# stm32l4x5_syscfg.c 17120936684SInès Varholstm32l4x5_syscfg_set_irq(int gpio, int line, int level) "irq from GPIO: %d, line: %d, level: %d" 17220936684SInès Varholstm32l4x5_syscfg_forward_exti(int irq) "irq %d forwarded to EXTI" 17320936684SInès Varholstm32l4x5_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " 17420936684SInès Varholstm32l4x5_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" 17520936684SInès Varhol 176c9948fddSInès Varhol# stm32l4x5_exti.c 177c9948fddSInès Varholstm32l4x5_exti_set_irq(int irq, int level) "Set EXTI: %d to %d" 178c9948fddSInès Varholstm32l4x5_exti_read(uint64_t addr, uint64_t data) "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" 179c9948fddSInès Varholstm32l4x5_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" 180c9948fddSInès Varhol 181d6b55a0fSArnaud Minier# stm32l4x5_rcc.c 182d6b55a0fSArnaud Minierstm32l4x5_rcc_read(uint64_t addr, uint32_t data) "RCC: Read <0x%" PRIx64 "> -> 0x%" PRIx32 183d6b55a0fSArnaud Minierstm32l4x5_rcc_write(uint64_t addr, uint32_t data) "RCC: Write <0x%" PRIx64 "> <- 0x%" PRIx32 184ec7d83acSArnaud Minierstm32l4x5_rcc_mux_enable(uint32_t mux_id) "RCC: Mux %d enabled" 185ec7d83acSArnaud Minierstm32l4x5_rcc_mux_disable(uint32_t mux_id) "RCC: Mux %d disabled" 186ec7d83acSArnaud Minierstm32l4x5_rcc_mux_set_factor(uint32_t mux_id, uint32_t old_multiplier, uint32_t new_multiplier, uint32_t old_divider, uint32_t new_divider) "RCC: Mux %d factor changed: multiplier (%u -> %u), divider (%u -> %u)" 187ec7d83acSArnaud Minierstm32l4x5_rcc_mux_set_src(uint32_t mux_id, uint32_t old_src, uint32_t new_src) "RCC: Mux %d source changed: from %u to %u" 188ec7d83acSArnaud Minierstm32l4x5_rcc_mux_update(uint32_t mux_id, uint32_t src, uint64_t src_freq, uint32_t multiplier, uint32_t divider) "RCC: Mux %d src %d update: src_freq %" PRIu64 " multiplier %" PRIu32 " divider %" PRIu32 1896487653eSArnaud Minierstm32l4x5_rcc_pll_set_vco_multiplier(uint32_t pll_id, uint32_t old_multiplier, uint32_t new_multiplier) "RCC: PLL %u: vco_multiplier changed (%u -> %u)" 1906487653eSArnaud Minierstm32l4x5_rcc_pll_channel_enable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u enabled" 1916487653eSArnaud Minierstm32l4x5_rcc_pll_channel_disable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u disabled" 1926487653eSArnaud Minierstm32l4x5_rcc_pll_set_channel_divider(uint32_t pll_id, uint32_t channel_id, uint32_t old_divider, uint32_t new_divider) "RCC: PLL %u, channel %u: divider changed (%u -> %u)" 1936487653eSArnaud Minierstm32l4x5_rcc_pll_update(uint32_t pll_id, uint32_t channel_id, uint64_t vco_freq, uint64_t old_freq, uint64_t new_freq) "RCC: PLL %d channel %d update: vco_freq %" PRIu64 " old_freq %" PRIu64 " new_freq %" PRIu64 194d6b55a0fSArnaud Minier 195500016e5SMarkus Armbruster# tz-mpc.c 196344f4b15SPeter Maydelltz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" 197344f4b15SPeter Maydelltz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" 198344f4b15SPeter Maydelltz_mpc_mem_blocked_read(uint64_t addr, unsigned size, bool secure) "TZ MPC blocked read: offset 0x%" PRIx64 " size %u secure %d" 199344f4b15SPeter Maydelltz_mpc_mem_blocked_write(uint64_t addr, uint64_t data, unsigned size, bool secure) "TZ MPC blocked write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" 200344f4b15SPeter Maydelltz_mpc_translate(uint64_t addr, int flags, const char *idx, const char *res) "TZ MPC translate: addr 0x%" PRIx64 " flags 0x%x iommu_idx %s: %s" 201dd29d068SPeter Maydelltz_mpc_iommu_notify(uint64_t addr) "TZ MPC iommu: notifying UNMAP/MAP for 0x%" PRIx64 202344f4b15SPeter Maydell 203500016e5SMarkus Armbruster# tz-msc.c 204211e701dSPeter Maydelltz_msc_reset(void) "TZ MSC: reset" 205211e701dSPeter Maydelltz_msc_cfg_nonsec(int level) "TZ MSC: cfg_nonsec = %d" 206211e701dSPeter Maydelltz_msc_cfg_sec_resp(int level) "TZ MSC: cfg_sec_resp = %d" 207211e701dSPeter Maydelltz_msc_irq_clear(int level) "TZ MSC: int_clear = %d" 208211e701dSPeter Maydelltz_msc_update_irq(int level) "TZ MSC: setting irq line to %d" 209211e701dSPeter Maydelltz_msc_access_blocked(uint64_t offset) "TZ MSC: offset 0x%" PRIx64 " access blocked" 210211e701dSPeter Maydell 211500016e5SMarkus Armbruster# tz-ppc.c 2129eb8040cSPeter Maydelltz_ppc_reset(void) "TZ PPC: reset" 2139eb8040cSPeter Maydelltz_ppc_cfg_nonsec(int n, int level) "TZ PPC: cfg_nonsec[%d] = %d" 2149eb8040cSPeter Maydelltz_ppc_cfg_ap(int n, int level) "TZ PPC: cfg_ap[%d] = %d" 2159eb8040cSPeter Maydelltz_ppc_cfg_sec_resp(int level) "TZ PPC: cfg_sec_resp = %d" 2169eb8040cSPeter Maydelltz_ppc_irq_enable(int level) "TZ PPC: int_enable = %d" 2179eb8040cSPeter Maydelltz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d" 2189eb8040cSPeter Maydelltz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d" 219f32408f3SDaniel P. Berrangétz_ppc_read_blocked(int n, uint64_t offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" PRIx64 " read (secure %d user %d) blocked" 220f32408f3SDaniel P. Berrangétz_ppc_write_blocked(int n, uint64_t offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" PRIx64 " write (secure %d user %d) blocked" 221de343bb6SPeter Maydell 222500016e5SMarkus Armbruster# iotkit-secctl.c 223de343bb6SPeter Maydelliotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u" 224de343bb6SPeter Maydelliotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u" 225de343bb6SPeter Maydelliotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" 226de343bb6SPeter Maydelliotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" 227781182e1SJean-Christophe Dubois 2283839aff8SBernhard Beschow# imx6_ccm.c 2293839aff8SBernhard Beschowimx6_analog_get_periph_clk(uint32_t freq) "freq = %u Hz" 2303839aff8SBernhard Beschowimx6_analog_get_pll2_clk(uint32_t freq) "freq = %u Hz" 2313839aff8SBernhard Beschowimx6_analog_get_pll2_pfd0_clk(uint32_t freq) "freq = %u Hz" 2323839aff8SBernhard Beschowimx6_analog_get_pll2_pfd2_clk(uint32_t freq) "freq = %u Hz" 2333839aff8SBernhard Beschowimx6_analog_read(const char *reg, uint32_t value) "reg[%s] => 0x%" PRIx32 2343839aff8SBernhard Beschowimx6_analog_write(const char *reg, uint32_t value) "reg[%s] <= 0x%" PRIx32 2353839aff8SBernhard Beschowimx6_ccm_get_ahb_clk(uint32_t freq) "freq = %u Hz" 2363839aff8SBernhard Beschowimx6_ccm_get_ipg_clk(uint32_t freq) "freq = %u Hz" 2373839aff8SBernhard Beschowimx6_ccm_get_per_clk(uint32_t freq) "freq = %u Hz" 2383839aff8SBernhard Beschowimx6_ccm_get_clock_frequency(unsigned clock, uint32_t freq) "(Clock = %d) = %u" 2393839aff8SBernhard Beschowimx6_ccm_read(const char *reg, uint32_t value) "reg[%s] => 0x%" PRIx32 2403839aff8SBernhard Beschowimx6_ccm_reset(void) "" 2413839aff8SBernhard Beschowimx6_ccm_write(const char *reg, uint32_t value) "reg[%s] <= 0x%" PRIx32 2423839aff8SBernhard Beschow 243500016e5SMarkus Armbruster# imx6ul_ccm.c 244794dcb54SPhilippe Mathieu-Daudéccm_entry(void) "" 245794dcb54SPhilippe Mathieu-Daudéccm_freq(uint32_t freq) "freq = %d" 246794dcb54SPhilippe Mathieu-Daudéccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d" 247794dcb54SPhilippe Mathieu-Daudéccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 248794dcb54SPhilippe Mathieu-Daudéccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 24975750e4dSPeter Maydell 25012517bc9SJean-Christophe Dubois# imx7_src.c 25112517bc9SJean-Christophe Duboisimx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 25212517bc9SJean-Christophe Duboisimx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 25312517bc9SJean-Christophe Dubois 254dec97760SMarkus Armbruster# iotkit-sysinfo.c 25575750e4dSPeter Maydelliotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 25675750e4dSPeter Maydelliotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 257dec97760SMarkus Armbruster 258dec97760SMarkus Armbruster# iotkit-sysctl.c 25975750e4dSPeter Maydelliotkit_sysctl_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 26075750e4dSPeter Maydelliotkit_sysctl_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 26175750e4dSPeter Maydelliotkit_sysctl_reset(void) "IoTKit SysCtl: reset" 2625aeb3689SPeter Maydell 2634239b311SPeter Maydell# armsse-cpu-pwrctrl.c 2644239b311SPeter Maydellarmsse_cpu_pwrctrl_read(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 2654239b311SPeter Maydellarmsse_cpu_pwrctrl_write(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 2664239b311SPeter Maydell 267500016e5SMarkus Armbruster# armsse-cpuid.c 2685aeb3689SPeter Maydellarmsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 2695aeb3689SPeter Maydellarmsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 270cdf63440SPeter Maydell 271500016e5SMarkus Armbruster# armsse-mhu.c 272cdf63440SPeter Maydellarmsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 273cdf63440SPeter Maydellarmsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 274118c82e7SEddie James 275118c82e7SEddie James# aspeed_xdma.c 276118c82e7SEddie Jamesaspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64 27719845504SPhilippe Mathieu-Daudé 278119df56bSTroy Lee# aspeed_i3c.c 279119df56bSTroy Leeaspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64 280119df56bSTroy Leeaspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64 281119df56bSTroy Leeaspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 282119df56bSTroy Leeaspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 283119df56bSTroy Lee 2843671342aSCédric Le Goater# aspeed_sdmc.c 2853671342aSCédric Le Goateraspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64 2863671342aSCédric Le Goateraspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64 2873671342aSCédric Le Goater 28855c57023SPeter Delevoryas# aspeed_peci.c 28955c57023SPeter Delevoryasaspeed_peci_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 29055c57023SPeter Delevoryasaspeed_peci_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 29155c57023SPeter Delevoryasaspeed_peci_raise_interrupt(uint32_t ctrl, uint32_t status) "ctrl 0x%" PRIx32 " status 0x%" PRIx32 29255c57023SPeter Delevoryas 293b15e402fSMarkus Armbruster# bcm2835_property.c 294b15e402fSMarkus Armbrusterbcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu" 295b15e402fSMarkus Armbruster 29619845504SPhilippe Mathieu-Daudé# bcm2835_mbox.c 29719845504SPhilippe Mathieu-Daudébcm2835_mbox_write(unsigned int size, uint64_t addr, uint64_t value) "mbox write sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 29819845504SPhilippe Mathieu-Daudébcm2835_mbox_read(unsigned int size, uint64_t addr, uint64_t value) "mbox read sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 29919845504SPhilippe Mathieu-Daudébcm2835_mbox_irq(unsigned level) "mbox irq:ARM level:%u" 300b2619c15SLaurent Vivier 301b2619c15SLaurent Vivier# mac_via.c 302b2619c15SLaurent Viviervia1_rtc_update_data_out(int count, int value) "count=%d value=0x%02x" 303b2619c15SLaurent Viviervia1_rtc_update_data_in(int count, int value) "count=%d value=0x%02x" 304b2619c15SLaurent Viviervia1_rtc_internal_status(int cmd, int alt, int value) "cmd=0x%02x alt=0x%02x value=0x%02x" 305b2619c15SLaurent Viviervia1_rtc_internal_cmd(int cmd) "cmd=0x%02x" 306b2619c15SLaurent Viviervia1_rtc_cmd_invalid(int value) "value=0x%02x" 307b2619c15SLaurent Viviervia1_rtc_internal_time(uint32_t time) "time=0x%08x" 308b2619c15SLaurent Viviervia1_rtc_internal_set_cmd(int cmd) "cmd=0x%02x" 309b2619c15SLaurent Viviervia1_rtc_internal_ignore_cmd(int cmd) "cmd=0x%02x" 310b2619c15SLaurent Viviervia1_rtc_internal_set_alt(int alt, int sector, int offset) "alt=0x%02x sector=%u offset=%u" 311b2619c15SLaurent Viviervia1_rtc_cmd_seconds_read(int reg, int value) "reg=%d value=0x%02x" 312b2619c15SLaurent Viviervia1_rtc_cmd_seconds_write(int reg, int value) "reg=%d value=0x%02x" 313b2619c15SLaurent Viviervia1_rtc_cmd_test_write(int value) "value=0x%02x" 314b2619c15SLaurent Viviervia1_rtc_cmd_wprotect_write(int value) "value=0x%02x" 315b2619c15SLaurent Viviervia1_rtc_cmd_pram_read(int addr, int value) "addr=%u value=0x%02x" 316b2619c15SLaurent Viviervia1_rtc_cmd_pram_write(int addr, int value) "addr=%u value=0x%02x" 317935cac9cSMark Cave-Aylandvia1_rtc_cmd_pram_sect_read(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=0x%x value=0x%02x" 318935cac9cSMark Cave-Aylandvia1_rtc_cmd_pram_sect_write(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=0x%x value=0x%02x" 319975fceddSMark Cave-Aylandvia1_adb_send(const char *state, uint8_t data, const char *vadbint) "state %s data=0x%02x vADBInt=%s" 320975fceddSMark Cave-Aylandvia1_adb_receive(const char *state, uint8_t data, const char *vadbint, int status, int index, int size) "state %s data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" 321975fceddSMark Cave-Aylandvia1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size) "data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" 32220069049SMark Cave-Aylandvia1_adb_netbsd_enum_hack(void) "using NetBSD enum hack" 323291bc180SMark Cave-Aylandvia1_auxmode(int mode) "setting auxmode to %d" 324366d2779SMark Cave-Aylandvia1_timer_hack_state(int state) "setting timer_hack_state to %d" 325d15188ddSPhilippe Mathieu-Daudé 326d15188ddSPhilippe Mathieu-Daudé# grlib_ahb_apb_pnp.c 32709d12c81SPeter Maydellgrlib_ahb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x" 32809d12c81SPeter Maydellgrlib_apb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "APB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x" 329b989b89fSPhilippe Mathieu-Daudé 330c1b29826SPhilippe Mathieu-Daudé# led.c 331c1b29826SPhilippe Mathieu-Daudéled_set_intensity(const char *color, const char *desc, uint8_t intensity_percent) "LED desc:'%s' color:%s intensity: %u%%" 3324aef4399SPhilippe Mathieu-Daudéled_change_intensity(const char *color, const char *desc, uint8_t old_intensity_percent, uint8_t new_intensity_percent) "LED desc:'%s' color:%s intensity %u%% -> %u%%" 333c1b29826SPhilippe Mathieu-Daudé 334fc14176bSLuc Michel# bcm2835_cprman.c 335fc14176bSLuc Michelbcm2835_cprman_read(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 336fc14176bSLuc Michelbcm2835_cprman_write(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 337fc14176bSLuc Michelbcm2835_cprman_write_invalid_magic(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 3380791bc02SLaurent Vivier 3390791bc02SLaurent Vivier# virt_ctrl.c 3400791bc02SLaurent Viviervirt_ctrl_read(void *dev, unsigned int addr, unsigned int size, uint64_t value) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 3410791bc02SLaurent Viviervirt_ctrl_write(void *dev, unsigned int addr, unsigned int size, uint64_t value) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 3420791bc02SLaurent Viviervirt_ctrl_reset(void *dev) "ctrl: %p" 3430791bc02SLaurent Viviervirt_ctrl_realize(void *dev) "ctrl: %p" 3440791bc02SLaurent Viviervirt_ctrl_instance_init(void *dev) "ctrl: %p" 34545f569a1SMark Cave-Ayland 34645f569a1SMark Cave-Ayland# lasi.c 34745f569a1SMark Cave-Aylandlasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d" 34845f569a1SMark Cave-Aylandlasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" 34945f569a1SMark Cave-Aylandlasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" 350e2fd695eSMark Cave-Ayland 351e2fd695eSMark Cave-Ayland# djmemc.c 352e2fd695eSMark Cave-Aylanddjmemc_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" 353e2fd695eSMark Cave-Aylanddjmemc_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" 354bdc2c77dSMark Cave-Ayland 355bdc2c77dSMark Cave-Ayland# iosb.c 356bdc2c77dSMark Cave-Aylandiosb_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" 357bdc2c77dSMark Cave-Aylandiosb_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" 358f944890dSJamin Lin 359f944890dSJamin Lin# aspeed_sli.c 360f944890dSJamin Linaspeed_sli_write(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 361f944890dSJamin Linaspeed_sli_read(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 362f944890dSJamin Linaspeed_sliio_write(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 363f944890dSJamin Linaspeed_sliio_read(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 364f944890dSJamin Lin 365