/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | mediatek,mt7621-sysc.yaml | 13 The MT7621 has a PLL controller from where the cpu clock is provided
|
H A D | microchip,mpfs-ccc.yaml | 31 The CCC PLL's have two input clocks. It is required that even if the input
|
H A D | samsung,s3c64xx-clock.txt | 31 - "fin_pll" - PLL input clock (xtal/extclk) - required,
|
H A D | imx7ulp-scg-clock.yaml | 56 - description: usb PLL
|
/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | mediatek,dsi-phy.yaml | 44 - description: PLL reference clock
|
H A D | nvidia,tegra210-xusb-padctl.yaml | 63 description: UTMI PLL power supply. Must supply 1.8 V. 66 description: PLLE reference PLL power supply. Must supply 1.05 V. 69 description: PCIe/USB3 PLL power supply. Must supply 1.05 V. 201 - description: PCIe PLL clock source 309 - description: SATA PLL clock source
|
/openbmc/linux/Documentation/devicetree/bindings/display/mediatek/ |
H A D | mediatek,dpi.yaml | 45 - description: DPI PLL
|
H A D | mediatek,dp.yaml | 18 of DP is generated by itself and we are not using other PLL to generate
|
H A D | mediatek,hdmi.yaml | 34 - description: HDMI PLL
|
/openbmc/linux/drivers/clk/rockchip/ |
H A D | clk-rv1126.c | 191 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 197 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 200 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 203 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 206 [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
|
H A D | clk-rk3308.c | 180 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 183 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 186 [vpll0] = PLL(pll_rk3328, PLL_VPLL0, "vpll0", mux_pll_p, 189 [vpll1] = PLL(pll_rk3328, PLL_VPLL1, "vpll1", mux_pll_p,
|
/openbmc/linux/Documentation/devicetree/bindings/display/ti/ |
H A D | ti,dra7-dss.txt | 20 Some DRA7xx SoCs have one dedicated video PLL, some have two. These properties
|
/openbmc/linux/Documentation/devicetree/bindings/iio/frequency/ |
H A D | adi,adf4377.yaml | 15 phased locked loop (PLL) with integrated voltage controlled oscillator (VCO)
|
/openbmc/linux/Documentation/devicetree/bindings/sound/ |
H A D | fsl,xcvr.yaml | 48 - description: PLL clock
|
H A D | wlf,wm8962.yaml | 47 description: PLL Supply
|
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
H A D | renesas,dsi-csi2-tx.yaml | 30 - description: PLL reference clock
|
H A D | chipone,icn6211.yaml | 43 description: A 1.8V/2.5V/3.3V supply that power the PLL.
|
/openbmc/linux/drivers/clk/samsung/ |
H A D | clk-exynos850.c | 207 PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 210 PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 213 PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", 781 PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 1076 PLL(pll_0818x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
|
/openbmc/linux/Documentation/devicetree/bindings/media/ |
H A D | imx.txt | 40 (the D-PHY clock), video_27m (D-PHY PLL reference
|
/openbmc/linux/Documentation/sound/soc/ |
H A D | clocking.rst | 14 (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
|
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
H A D | Kconfig | 442 This number is the reference clock frequency of core PLL. 443 For most platforms, the core PLL and Platform PLL have the same 455 Platform PLL, in another word:
|
/openbmc/linux/arch/arm/mach-sa1100/ |
H A D | sleep.S | 53 @ delay 90us and set CPU PLL to lowest speed
|
/openbmc/linux/Documentation/devicetree/bindings/display/tegra/ |
H A D | nvidia,tegra20-hdmi.yaml | 66 description: regulator for PLL
|
/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | am3874-iceboard.dts | 354 /* The PLL doesn't react well to the SPI controller reset, so 369 DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */ 370 DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */
|
/openbmc/linux/Documentation/devicetree/bindings/pci/ |
H A D | amlogic,axg-pcie.yaml | 54 - description: PCIe GEN 100M PLL clock
|