19273cf7dSJitao Shi# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 29273cf7dSJitao Shi%YAML 1.2 39273cf7dSJitao Shi--- 49273cf7dSJitao Shi$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# 59273cf7dSJitao Shi$schema: http://devicetree.org/meta-schemas/core.yaml# 69273cf7dSJitao Shi 7f294c89fSBo-Chen Chentitle: MediaTek DPI and DP_INTF Controller 89273cf7dSJitao Shi 99273cf7dSJitao Shimaintainers: 109273cf7dSJitao Shi - CK Hu <ck.hu@mediatek.com> 119273cf7dSJitao Shi - Jitao shi <jitao.shi@mediatek.com> 129273cf7dSJitao Shi 139273cf7dSJitao Shidescription: | 14f294c89fSBo-Chen Chen The MediaTek DPI and DP_INTF function blocks are a sink of the display 15e32895fcSMarkus Schneider-Pargmann subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a 16e32895fcSMarkus Schneider-Pargmann parallel output bus. 179273cf7dSJitao Shi 189273cf7dSJitao Shiproperties: 199273cf7dSJitao Shi compatible: 20*b84c6b26SAngeloGioacchino Del Regno oneOf: 21*b84c6b26SAngeloGioacchino Del Regno - enum: 229273cf7dSJitao Shi - mediatek,mt2701-dpi 239273cf7dSJitao Shi - mediatek,mt7623-dpi 249273cf7dSJitao Shi - mediatek,mt8173-dpi 259273cf7dSJitao Shi - mediatek,mt8183-dpi 2652136021SXinlei Lee - mediatek,mt8186-dpi 27c1a26a98Sxinlei lee - mediatek,mt8188-dp-intf 2861865513SJitao Shi - mediatek,mt8192-dpi 29e32895fcSMarkus Schneider-Pargmann - mediatek,mt8195-dp-intf 30*b84c6b26SAngeloGioacchino Del Regno - items: 31*b84c6b26SAngeloGioacchino Del Regno - enum: 32*b84c6b26SAngeloGioacchino Del Regno - mediatek,mt6795-dpi 33*b84c6b26SAngeloGioacchino Del Regno - const: mediatek,mt8183-dpi 349273cf7dSJitao Shi 359273cf7dSJitao Shi reg: 369273cf7dSJitao Shi maxItems: 1 379273cf7dSJitao Shi 389273cf7dSJitao Shi interrupts: 399273cf7dSJitao Shi maxItems: 1 409273cf7dSJitao Shi 419273cf7dSJitao Shi clocks: 429273cf7dSJitao Shi items: 439273cf7dSJitao Shi - description: Pixel Clock 449273cf7dSJitao Shi - description: Engine Clock 459273cf7dSJitao Shi - description: DPI PLL 469273cf7dSJitao Shi 479273cf7dSJitao Shi clock-names: 489273cf7dSJitao Shi items: 499273cf7dSJitao Shi - const: pixel 509273cf7dSJitao Shi - const: engine 519273cf7dSJitao Shi - const: pll 529273cf7dSJitao Shi 539273cf7dSJitao Shi pinctrl-0: true 549273cf7dSJitao Shi pinctrl-1: true 559273cf7dSJitao Shi 569273cf7dSJitao Shi pinctrl-names: 579273cf7dSJitao Shi items: 589273cf7dSJitao Shi - const: default 599273cf7dSJitao Shi - const: sleep 609273cf7dSJitao Shi 619273cf7dSJitao Shi port: 62be7507bdSRob Herring $ref: /schemas/graph.yaml#/properties/port 639273cf7dSJitao Shi description: 64be7507bdSRob Herring Output port node. This port should be connected to the input port of an 65e32895fcSMarkus Schneider-Pargmann attached HDMI, LVDS or DisplayPort encoder chip. 669273cf7dSJitao Shi 679273cf7dSJitao Shirequired: 689273cf7dSJitao Shi - compatible 699273cf7dSJitao Shi - reg 709273cf7dSJitao Shi - interrupts 719273cf7dSJitao Shi - clocks 729273cf7dSJitao Shi - clock-names 739273cf7dSJitao Shi - port 749273cf7dSJitao Shi 759273cf7dSJitao ShiadditionalProperties: false 769273cf7dSJitao Shi 779273cf7dSJitao Shiexamples: 789273cf7dSJitao Shi - | 799273cf7dSJitao Shi #include <dt-bindings/interrupt-controller/arm-gic.h> 809273cf7dSJitao Shi #include <dt-bindings/clock/mt8173-clk.h> 81bff4e302SAngeloGioacchino Del Regno 829273cf7dSJitao Shi dpi0: dpi@1401d000 { 839273cf7dSJitao Shi compatible = "mediatek,mt8173-dpi"; 849273cf7dSJitao Shi reg = <0x1401d000 0x1000>; 859273cf7dSJitao Shi interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 869273cf7dSJitao Shi clocks = <&mmsys CLK_MM_DPI_PIXEL>, 879273cf7dSJitao Shi <&mmsys CLK_MM_DPI_ENGINE>, 889273cf7dSJitao Shi <&apmixedsys CLK_APMIXED_TVDPLL>; 899273cf7dSJitao Shi clock-names = "pixel", "engine", "pll"; 909273cf7dSJitao Shi pinctrl-names = "default", "sleep"; 919273cf7dSJitao Shi pinctrl-0 = <&dpi_pin_func>; 929273cf7dSJitao Shi pinctrl-1 = <&dpi_pin_idle>; 939273cf7dSJitao Shi 949273cf7dSJitao Shi port { 959273cf7dSJitao Shi dpi0_out: endpoint { 969273cf7dSJitao Shi remote-endpoint = <&hdmi0_in>; 979273cf7dSJitao Shi }; 989273cf7dSJitao Shi }; 999273cf7dSJitao Shi }; 1009273cf7dSJitao Shi 1019273cf7dSJitao Shi... 102