1bb9e0771SSteve LongerbeamFreescale i.MX Media Video Device
2bb9e0771SSteve Longerbeam=================================
3bb9e0771SSteve Longerbeam
4bb9e0771SSteve LongerbeamVideo Media Controller node
5bb9e0771SSteve Longerbeam---------------------------
6bb9e0771SSteve Longerbeam
7bb9e0771SSteve LongerbeamThis is the media controller node for video capture support. It is a
8bb9e0771SSteve Longerbeamvirtual device that lists the camera serial interface nodes that the
9bb9e0771SSteve Longerbeammedia device will control.
10bb9e0771SSteve Longerbeam
11bb9e0771SSteve LongerbeamRequired properties:
12bb9e0771SSteve Longerbeam- compatible : "fsl,imx-capture-subsystem";
13bb9e0771SSteve Longerbeam- ports      : Should contain a list of phandles pointing to camera
14bb9e0771SSteve Longerbeam		sensor interface ports of IPU devices
15bb9e0771SSteve Longerbeam
16bb9e0771SSteve Longerbeamexample:
17bb9e0771SSteve Longerbeam
18bb9e0771SSteve Longerbeamcapture-subsystem {
19bb9e0771SSteve Longerbeam	compatible = "fsl,imx-capture-subsystem";
20bb9e0771SSteve Longerbeam	ports = <&ipu1_csi0>, <&ipu1_csi1>;
21bb9e0771SSteve Longerbeam};
22bb9e0771SSteve Longerbeam
23bb9e0771SSteve Longerbeam
24bb9e0771SSteve Longerbeammipi_csi2 node
25bb9e0771SSteve Longerbeam--------------
26bb9e0771SSteve Longerbeam
27bb9e0771SSteve LongerbeamThis is the device node for the MIPI CSI-2 Receiver core in the i.MX
28bb9e0771SSteve LongerbeamSoC. This is a Synopsys Designware MIPI CSI-2 host controller core
29bb9e0771SSteve Longerbeamcombined with a D-PHY core mixed into the same register block. In
30bb9e0771SSteve Longerbeamaddition this device consists of an i.MX-specific "CSI2IPU gasket"
31bb9e0771SSteve Longerbeamglue logic, also controlled from the same register block. The CSI2IPU
32bb9e0771SSteve Longerbeamgasket demultiplexes the four virtual channel streams from the host
33bb9e0771SSteve Longerbeamcontroller's 32-bit output image bus onto four 16-bit parallel busses
34bb9e0771SSteve Longerbeamto the i.MX IPU CSIs.
35bb9e0771SSteve Longerbeam
36bb9e0771SSteve LongerbeamRequired properties:
37bb9e0771SSteve Longerbeam- compatible	: "fsl,imx6-mipi-csi2";
38bb9e0771SSteve Longerbeam- reg           : physical base address and length of the register set;
39bb9e0771SSteve Longerbeam- clocks	: the MIPI CSI-2 receiver requires three clocks: hsi_tx
40bb9e0771SSteve Longerbeam		  (the D-PHY clock), video_27m (D-PHY PLL reference
41bb9e0771SSteve Longerbeam		  clock), and eim_podf;
42bb9e0771SSteve Longerbeam- clock-names	: must contain "dphy", "ref", "pix";
43bb9e0771SSteve Longerbeam- port@*        : five port nodes must exist, containing endpoints
44bb9e0771SSteve Longerbeam		  connecting to the source and sink devices according to
45bb9e0771SSteve Longerbeam		  of_graph bindings. The first port is an input port,
46bb9e0771SSteve Longerbeam		  connecting with a MIPI CSI-2 source, and ports 1
47bb9e0771SSteve Longerbeam		  through 4 are output ports connecting with parallel
48bb9e0771SSteve Longerbeam		  bus sink endpoint nodes and correspond to the four
49bb9e0771SSteve Longerbeam		  MIPI CSI-2 virtual channel outputs.
50bb9e0771SSteve Longerbeam
51bb9e0771SSteve LongerbeamOptional properties:
52bb9e0771SSteve Longerbeam- interrupts	: must contain two level-triggered interrupts,
53bb9e0771SSteve Longerbeam		  in order: 100 and 101;
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