| /openbmc/u-boot/include/configs/ |
| H A D | bcm_ep_board.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | ti_omap3_common.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | vexpress_common.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | at91-sama5_common.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | rk3036_common.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | rcar-gen2-common.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | pcm052.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | kzm9g.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | smdkc100.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | colibri_vf.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | vf610twr.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | ti816x_evm.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | rk3288_common.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | cm_t3517.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | ti814x_evm.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | nokia_rx51.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | tao3530.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | s5p_goni.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | tricorder.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | am3517_crane.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | cm_t35.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | am3517_evm.h | 3709844f Wed Jan 27 01:46:11 CST 2016 Albert ARIBAUD <albert.u.boot@aribaud.net> armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
|