1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2e7b860faSSanchayan Maity /* 3b891d010SMarcel Ziswiler * Copyright 2015-2016 Toradex, Inc. 4e7b860faSSanchayan Maity * 5b891d010SMarcel Ziswiler * Configuration settings for the Toradex VF50/VF61 modules. 6e7b860faSSanchayan Maity * 7e7b860faSSanchayan Maity * Based on vf610twr.h: 8e7b860faSSanchayan Maity * Copyright 2013 Freescale Semiconductor, Inc. 9e7b860faSSanchayan Maity */ 10e7b860faSSanchayan Maity 11e7b860faSSanchayan Maity #ifndef __CONFIG_H 12e7b860faSSanchayan Maity #define __CONFIG_H 13e7b860faSSanchayan Maity 14e7b860faSSanchayan Maity #include <asm/arch/imx-regs.h> 15e7b860faSSanchayan Maity 1618fb0e3cSGong Qianyu #define CONFIG_SYS_FSL_CLK 17e7b860faSSanchayan Maity 18e7b860faSSanchayan Maity #define CONFIG_SKIP_LOWLEVEL_INIT 19e7b860faSSanchayan Maity 20e7b860faSSanchayan Maity #ifdef CONFIG_CMD_FUSE 21e7b860faSSanchayan Maity #define CONFIG_MXC_OCOTP 22e7b860faSSanchayan Maity #endif 23e7b860faSSanchayan Maity 2480b9c3bbSStefan Agner #ifdef CONFIG_VIDEO_FSL_DCU_FB 2580b9c3bbSStefan Agner #define CONFIG_SPLASH_SCREEN_ALIGN 2680b9c3bbSStefan Agner #define CONFIG_VIDEO_LOGO 2780b9c3bbSStefan Agner #define CONFIG_VIDEO_BMP_LOGO 2880b9c3bbSStefan Agner #define CONFIG_SYS_FSL_DCU_LE 2980b9c3bbSStefan Agner 3080b9c3bbSStefan Agner #define CONFIG_SYS_DCU_ADDR DCU0_BASE_ADDR 3180b9c3bbSStefan Agner #define DCU_LAYER_MAX_NUM 64 3280b9c3bbSStefan Agner #endif 3380b9c3bbSStefan Agner 34e7b860faSSanchayan Maity /* Size of malloc() pool */ 35e7b860faSSanchayan Maity #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) 36e7b860faSSanchayan Maity 37e7b860faSSanchayan Maity /* Allow to overwrite serial and ethaddr */ 38e7b860faSSanchayan Maity #define CONFIG_ENV_OVERWRITE 39e7b860faSSanchayan Maity 40e7b860faSSanchayan Maity /* NAND support */ 418fca2d8cSStefan Agner #define CONFIG_SYS_NAND_ONFI_DETECTION 42e7b860faSSanchayan Maity #define CONFIG_SYS_MAX_NAND_DEVICE 1 43e7b860faSSanchayan Maity #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 44e7b860faSSanchayan Maity 45e7b860faSSanchayan Maity /* Dynamic MTD partition support */ 46e7b860faSSanchayan Maity 47e7b860faSSanchayan Maity #define CONFIG_SYS_FSL_ESDHC_ADDR 0 48e7b860faSSanchayan Maity #define CONFIG_SYS_FSL_ESDHC_NUM 1 49e7b860faSSanchayan Maity 50e7b860faSSanchayan Maity #define CONFIG_FEC_MXC 51e7b860faSSanchayan Maity #define IMX_FEC_BASE ENET1_BASE_ADDR 52e7b860faSSanchayan Maity #define CONFIG_FEC_XCV_TYPE RMII 53e7b860faSSanchayan Maity #define CONFIG_FEC_MXC_PHYADDR 0 54e7b860faSSanchayan Maity 55e7b860faSSanchayan Maity #define CONFIG_IPADDR 192.168.10.2 56e7b860faSSanchayan Maity #define CONFIG_NETMASK 255.255.255.0 57e7b860faSSanchayan Maity #define CONFIG_SERVERIP 192.168.10.1 58e7b860faSSanchayan Maity 59e7b860faSSanchayan Maity #define CONFIG_LOADADDR 0x80008000 60e7b860faSSanchayan Maity #define CONFIG_FDTADDR 0x84000000 61e7b860faSSanchayan Maity 62e7b860faSSanchayan Maity /* We boot from the gfxRAM area of the OCRAM. */ 63c0f432c3SStefan Agner #define CONFIG_BOARD_SIZE_LIMIT 520192 64e7b860faSSanchayan Maity 65e7b860faSSanchayan Maity #define SD_BOOTCMD \ 66e7b860faSSanchayan Maity "sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \ 67e7b860faSSanchayan Maity "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \ 68e7b860faSSanchayan Maity "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ 69e7b860faSSanchayan Maity "load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \ 70e7b860faSSanchayan Maity "load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \ 71faf1e62bSSanchayan Maity "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ 72e7b860faSSanchayan Maity 73e7b860faSSanchayan Maity #define NFS_BOOTCMD \ 74e7b860faSSanchayan Maity "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ 75e7b860faSSanchayan Maity "nfsboot=run setup; " \ 76e7b860faSSanchayan Maity "setenv bootargs ${defargs} ${nfsargs} ${mtdparts} " \ 77e7b860faSSanchayan Maity "${setupargs} ${vidargs}; echo Booting from NFS...;" \ 78e7b860faSSanchayan Maity "dhcp ${kernel_addr_r} && " \ 79e7b860faSSanchayan Maity "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ 80faf1e62bSSanchayan Maity "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ 81e7b860faSSanchayan Maity 82e7b860faSSanchayan Maity #define UBI_BOOTCMD \ 83e7b860faSSanchayan Maity "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ 84e7b860faSSanchayan Maity "ubi.fm_autoconvert=1\0" \ 85e7b860faSSanchayan Maity "ubiboot=run setup; " \ 86e7b860faSSanchayan Maity "setenv bootargs ${defargs} ${ubiargs} ${mtdparts} " \ 87e7b860faSSanchayan Maity "${setupargs} ${vidargs}; echo Booting from NAND...; " \ 883ed82d6fSSanchayan Maity "ubi part ubi && " \ 893ed82d6fSSanchayan Maity "ubi read ${kernel_addr_r} kernel && " \ 903ed82d6fSSanchayan Maity "ubi read ${fdt_addr_r} dtb && " \ 91faf1e62bSSanchayan Maity "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ 92e7b860faSSanchayan Maity 93e7b860faSSanchayan Maity #define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot" 94e7b860faSSanchayan Maity 95bba97cd2SSanchayan Maity #define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4" 96bba97cd2SSanchayan Maity 97e7b860faSSanchayan Maity #define CONFIG_EXTRA_ENV_SETTINGS \ 98e7b860faSSanchayan Maity "kernel_addr_r=0x82000000\0" \ 99e7b860faSSanchayan Maity "fdt_addr_r=0x84000000\0" \ 100e7b860faSSanchayan Maity "kernel_file=zImage\0" \ 101e7b860faSSanchayan Maity "fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \ 102e7b860faSSanchayan Maity "fdt_board=eval-v3\0" \ 103faf1e62bSSanchayan Maity "fdt_fixup=;\0" \ 104e7b860faSSanchayan Maity "defargs=\0" \ 105e7b860faSSanchayan Maity "console=ttyLP0\0" \ 106e7b860faSSanchayan Maity "setup=setenv setupargs " \ 107e7b860faSSanchayan Maity "console=tty1 console=${console}" \ 108e7b860faSSanchayan Maity ",${baudrate}n8 ${memargs}\0" \ 109e7b860faSSanchayan Maity "setsdupdate=mmc rescan && set interface mmc && " \ 110e7b860faSSanchayan Maity "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ 111e7b860faSSanchayan Maity "source ${loadaddr}\0" \ 112e7b860faSSanchayan Maity "setusbupdate=usb start && set interface usb && " \ 113e7b860faSSanchayan Maity "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ 114e7b860faSSanchayan Maity "source ${loadaddr}\0" \ 115e7b860faSSanchayan Maity "setupdate=run setsdupdate || run setusbupdate\0" \ 11643ede0bcSTom Rini "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 117bba97cd2SSanchayan Maity "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ 11880b9c3bbSStefan Agner "video-mode=dcufb:640x480-16@60,monitor=lcd\0" \ 11980b9c3bbSStefan Agner "splashpos=m,m\0" \ 120e7b860faSSanchayan Maity SD_BOOTCMD \ 121e7b860faSSanchayan Maity NFS_BOOTCMD \ 122e7b860faSSanchayan Maity UBI_BOOTCMD 123e7b860faSSanchayan Maity 124e7b860faSSanchayan Maity /* Miscellaneous configurable options */ 125aa5a0d98SSanchayan Maity #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 126e7b860faSSanchayan Maity #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 127e7b860faSSanchayan Maity 128e7b860faSSanchayan Maity #define CONFIG_SYS_MEMTEST_START 0x80010000 129e7b860faSSanchayan Maity #define CONFIG_SYS_MEMTEST_END 0x87C00000 130e7b860faSSanchayan Maity 131e7b860faSSanchayan Maity #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 132e7b860faSSanchayan Maity #define CONFIG_SYS_HZ 1000 133e7b860faSSanchayan Maity 134e7b860faSSanchayan Maity /* Physical memory map */ 135e7b860faSSanchayan Maity #define PHYS_SDRAM (0x80000000) 136e7b860faSSanchayan Maity #define PHYS_SDRAM_SIZE (256 * 1024 * 1024) 137e7b860faSSanchayan Maity 138e7b860faSSanchayan Maity #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 139e7b860faSSanchayan Maity #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 140e7b860faSSanchayan Maity #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 141e7b860faSSanchayan Maity 142e7b860faSSanchayan Maity #define CONFIG_SYS_INIT_SP_OFFSET \ 143e7b860faSSanchayan Maity (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 144e7b860faSSanchayan Maity #define CONFIG_SYS_INIT_SP_ADDR \ 145e7b860faSSanchayan Maity (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 146e7b860faSSanchayan Maity 147e7b860faSSanchayan Maity /* Environment organization */ 148e7b860faSSanchayan Maity 149e7b860faSSanchayan Maity #ifdef CONFIG_ENV_IS_IN_MMC 150e7b860faSSanchayan Maity #define CONFIG_SYS_MMC_ENV_DEV 0 151e7b860faSSanchayan Maity #define CONFIG_ENV_OFFSET (12 * 64 * 1024) 152e7b860faSSanchayan Maity #define CONFIG_ENV_SIZE (8 * 1024) 153e7b860faSSanchayan Maity #endif 154e7b860faSSanchayan Maity 155e7b860faSSanchayan Maity #ifdef CONFIG_ENV_IS_IN_NAND 156e7b860faSSanchayan Maity #define CONFIG_ENV_SIZE (64 * 2048) 157e7b860faSSanchayan Maity #define CONFIG_ENV_RANGE (4 * 64 * 2048) 158e7b860faSSanchayan Maity #define CONFIG_ENV_OFFSET (12 * 64 * 2048) 159e7b860faSSanchayan Maity #endif 160e7b860faSSanchayan Maity 161bba97cd2SSanchayan Maity /* USB Host Support */ 162bba97cd2SSanchayan Maity #define CONFIG_USB_EHCI_VF 163bba97cd2SSanchayan Maity #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 164bba97cd2SSanchayan Maity #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 165bba97cd2SSanchayan Maity 166bba97cd2SSanchayan Maity /* USB DFU */ 167bba97cd2SSanchayan Maity #define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024 * 1024) 168bba97cd2SSanchayan Maity 169bba97cd2SSanchayan Maity /* USB Storage */ 170bba97cd2SSanchayan Maity 171e7b860faSSanchayan Maity #endif /* __CONFIG_H */ 172