1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 236b4e2ddSMike Rapoport /* 39fc376beSNikita Kiryanov * (C) Copyright 2011 CompuLab, Ltd. 436b4e2ddSMike Rapoport * Mike Rapoport <mike@compulab.co.il> 5dccd9a0bSIgor Grinberg * Igor Grinberg <grinberg@compulab.co.il> 636b4e2ddSMike Rapoport * 736b4e2ddSMike Rapoport * Based on omap3_beagle.h 836b4e2ddSMike Rapoport * (C) Copyright 2006-2008 936b4e2ddSMike Rapoport * Texas Instruments. 1036b4e2ddSMike Rapoport * Richard Woodruff <r-woodruff2@ti.com> 1136b4e2ddSMike Rapoport * Syed Mohammed Khasim <x0khasim@ti.com> 1236b4e2ddSMike Rapoport * 13b65a77a8SIgor Grinberg * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 1436b4e2ddSMike Rapoport */ 1536b4e2ddSMike Rapoport 1636b4e2ddSMike Rapoport #ifndef __CONFIG_H 1736b4e2ddSMike Rapoport #define __CONFIG_H 1836b4e2ddSMike Rapoport 193709844fSAlbert ARIBAUD #define CONFIG_SYS_CACHELINE_SIZE 64 203709844fSAlbert ARIBAUD 2136b4e2ddSMike Rapoport /* 2236b4e2ddSMike Rapoport * High Level Configuration Options 2336b4e2ddSMike Rapoport */ 249fc376beSNikita Kiryanov #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 2536b4e2ddSMike Rapoport 2636b4e2ddSMike Rapoport #include <asm/arch/cpu.h> /* get chip and board defs */ 27987ec585SNishanth Menon #include <asm/arch/omap.h> 2836b4e2ddSMike Rapoport 2936b4e2ddSMike Rapoport /* Clock Defines */ 3036b4e2ddSMike Rapoport #define V_OSCK 26000000 /* Clock output from T2 */ 3136b4e2ddSMike Rapoport #define V_SCLK (V_OSCK >> 1) 3236b4e2ddSMike Rapoport 339fc376beSNikita Kiryanov #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 349fc376beSNikita Kiryanov #define CONFIG_SETUP_MEMORY_TAGS 359fc376beSNikita Kiryanov #define CONFIG_INITRD_TAG 369fc376beSNikita Kiryanov #define CONFIG_REVISION_TAG 3782309250SNikita Kiryanov #define CONFIG_SERIAL_TAG 3836b4e2ddSMike Rapoport 3936b4e2ddSMike Rapoport /* 4036b4e2ddSMike Rapoport * Size of malloc() pool 4136b4e2ddSMike Rapoport */ 42390cdcdaSIgor Grinberg #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 4336b4e2ddSMike Rapoport /* Sector */ 4436b4e2ddSMike Rapoport #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 4536b4e2ddSMike Rapoport 4636b4e2ddSMike Rapoport /* 4736b4e2ddSMike Rapoport * Hardware drivers 4836b4e2ddSMike Rapoport */ 4936b4e2ddSMike Rapoport 5036b4e2ddSMike Rapoport /* 5136b4e2ddSMike Rapoport * NS16550 Configuration 5236b4e2ddSMike Rapoport */ 5336b4e2ddSMike Rapoport #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 5436b4e2ddSMike Rapoport 5536b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_SERIAL 5636b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_REG_SIZE (-4) 5736b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 5836b4e2ddSMike Rapoport 5936b4e2ddSMike Rapoport /* 6036b4e2ddSMike Rapoport * select serial console configuration 6136b4e2ddSMike Rapoport */ 6236b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 6336b4e2ddSMike Rapoport 6436b4e2ddSMike Rapoport /* allow to overwrite serial and ethaddr */ 6536b4e2ddSMike Rapoport #define CONFIG_ENV_OVERWRITE 6636b4e2ddSMike Rapoport #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 6736b4e2ddSMike Rapoport 115200} 689fc376beSNikita Kiryanov 6936b4e2ddSMike Rapoport /* USB device configuration */ 709fc376beSNikita Kiryanov #define CONFIG_USB_DEVICE 719fc376beSNikita Kiryanov #define CONFIG_USB_TTY 7236b4e2ddSMike Rapoport 7336b4e2ddSMike Rapoport /* commands to include */ 7436b4e2ddSMike Rapoport 756789e84eSHeiko Schocher #define CONFIG_SYS_I2C 7682309250SNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 7782309250SNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 7852658fdaSNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_BUS 0 7979874ae9SNikita Kiryanov #define CONFIG_I2C_MULTI_BUS 8036b4e2ddSMike Rapoport 8136b4e2ddSMike Rapoport /* 8236b4e2ddSMike Rapoport * TWL4030 8336b4e2ddSMike Rapoport */ 8436b4e2ddSMike Rapoport 8536b4e2ddSMike Rapoport /* 8636b4e2ddSMike Rapoport * Board NAND Info. 8736b4e2ddSMike Rapoport */ 8836b4e2ddSMike Rapoport #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 8936b4e2ddSMike Rapoport /* to access nand at */ 9036b4e2ddSMike Rapoport /* CS0 */ 9136b4e2ddSMike Rapoport #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 9236b4e2ddSMike Rapoport /* devices */ 937bb6e29bSStefan Roese 9436b4e2ddSMike Rapoport /* Environment information */ 9536b4e2ddSMike Rapoport #define CONFIG_EXTRA_ENV_SETTINGS \ 9636b4e2ddSMike Rapoport "loadaddr=0x82000000\0" \ 9736b4e2ddSMike Rapoport "usbtty=cdc_acm\0" \ 98f3ef3609SNikita Kiryanov "console=ttyO2,115200n8\0" \ 9936b4e2ddSMike Rapoport "mpurate=500\0" \ 10036b4e2ddSMike Rapoport "vram=12M\0" \ 10136b4e2ddSMike Rapoport "dvimode=1024x768MR-16@60\0" \ 10236b4e2ddSMike Rapoport "defaultdisplay=dvi\0" \ 10336b4e2ddSMike Rapoport "mmcdev=0\0" \ 10436b4e2ddSMike Rapoport "mmcroot=/dev/mmcblk0p2 rw\0" \ 1050b800a6bSIgor Grinberg "mmcrootfstype=ext4 rootwait\0" \ 10636b4e2ddSMike Rapoport "nandroot=/dev/mtdblock4 rw\0" \ 1070b800a6bSIgor Grinberg "nandrootfstype=ubifs\0" \ 10836b4e2ddSMike Rapoport "mmcargs=setenv bootargs console=${console} " \ 10936b4e2ddSMike Rapoport "mpurate=${mpurate} " \ 11036b4e2ddSMike Rapoport "vram=${vram} " \ 11136b4e2ddSMike Rapoport "omapfb.mode=dvi:${dvimode} " \ 11236b4e2ddSMike Rapoport "omapdss.def_disp=${defaultdisplay} " \ 11336b4e2ddSMike Rapoport "root=${mmcroot} " \ 11436b4e2ddSMike Rapoport "rootfstype=${mmcrootfstype}\0" \ 11536b4e2ddSMike Rapoport "nandargs=setenv bootargs console=${console} " \ 11636b4e2ddSMike Rapoport "mpurate=${mpurate} " \ 11736b4e2ddSMike Rapoport "vram=${vram} " \ 11836b4e2ddSMike Rapoport "omapfb.mode=dvi:${dvimode} " \ 11936b4e2ddSMike Rapoport "omapdss.def_disp=${defaultdisplay} " \ 12036b4e2ddSMike Rapoport "root=${nandroot} " \ 12136b4e2ddSMike Rapoport "rootfstype=${nandrootfstype}\0" \ 12236b4e2ddSMike Rapoport "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 12336b4e2ddSMike Rapoport "bootscript=echo Running bootscript from mmc ...; " \ 12436b4e2ddSMike Rapoport "source ${loadaddr}\0" \ 12536b4e2ddSMike Rapoport "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 12636b4e2ddSMike Rapoport "mmcboot=echo Booting from mmc ...; " \ 12736b4e2ddSMike Rapoport "run mmcargs; " \ 12836b4e2ddSMike Rapoport "bootm ${loadaddr}\0" \ 12936b4e2ddSMike Rapoport "nandboot=echo Booting from nand ...; " \ 13036b4e2ddSMike Rapoport "run nandargs; " \ 1310b800a6bSIgor Grinberg "nand read ${loadaddr} 2a0000 400000; " \ 13236b4e2ddSMike Rapoport "bootm ${loadaddr}\0" \ 13336b4e2ddSMike Rapoport 13436b4e2ddSMike Rapoport #define CONFIG_BOOTCOMMAND \ 13566968110SAndrew Bradford "mmc dev ${mmcdev}; if mmc rescan; then " \ 13636b4e2ddSMike Rapoport "if run loadbootscript; then " \ 13736b4e2ddSMike Rapoport "run bootscript; " \ 13836b4e2ddSMike Rapoport "else " \ 13936b4e2ddSMike Rapoport "if run loaduimage; then " \ 14036b4e2ddSMike Rapoport "run mmcboot; " \ 14136b4e2ddSMike Rapoport "else run nandboot; " \ 14236b4e2ddSMike Rapoport "fi; " \ 14336b4e2ddSMike Rapoport "fi; " \ 14436b4e2ddSMike Rapoport "else run nandboot; fi" 14536b4e2ddSMike Rapoport 14636b4e2ddSMike Rapoport /* 14736b4e2ddSMike Rapoport * Miscellaneous configurable options 14836b4e2ddSMike Rapoport */ 14941d7e702SIgor Grinberg #define CONFIG_TIMESTAMP 15041d7e702SIgor Grinberg #define CONFIG_SYS_AUTOLOAD "no" 15136b4e2ddSMike Rapoport 15236b4e2ddSMike Rapoport #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 15336b4e2ddSMike Rapoport /* works on */ 15436b4e2ddSMike Rapoport #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 15536b4e2ddSMike Rapoport 0x01F00000) /* 31MB */ 15636b4e2ddSMike Rapoport 15736b4e2ddSMike Rapoport #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 15836b4e2ddSMike Rapoport /* load address */ 15936b4e2ddSMike Rapoport 16036b4e2ddSMike Rapoport /* 16136b4e2ddSMike Rapoport * OMAP3 has 12 GP timers, they can be driven by the system clock 16236b4e2ddSMike Rapoport * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 16336b4e2ddSMike Rapoport * This rate is divided by a local divisor. 16436b4e2ddSMike Rapoport */ 16536b4e2ddSMike Rapoport #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 16636b4e2ddSMike Rapoport #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 16736b4e2ddSMike Rapoport 16836b4e2ddSMike Rapoport /*----------------------------------------------------------------------- 16936b4e2ddSMike Rapoport * Physical Memory Map 17036b4e2ddSMike Rapoport */ 17136b4e2ddSMike Rapoport #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 17236b4e2ddSMike Rapoport 17336b4e2ddSMike Rapoport /*----------------------------------------------------------------------- 17436b4e2ddSMike Rapoport * FLASH and environment organization 17536b4e2ddSMike Rapoport */ 17636b4e2ddSMike Rapoport 17736b4e2ddSMike Rapoport /* **** PISMO SUPPORT *** */ 17836b4e2ddSMike Rapoport /* Monitor at start of flash */ 17936b4e2ddSMike Rapoport #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 1803530a35dSIgor Grinberg #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 18136b4e2ddSMike Rapoport 1827672d9d5SAdam Ford #define CONFIG_ENV_OFFSET 0x260000 1837672d9d5SAdam Ford #define CONFIG_ENV_ADDR 0x260000 18436b4e2ddSMike Rapoport 18536b4e2ddSMike Rapoport /* additions for new relocation code, must be added to all boards */ 18636b4e2ddSMike Rapoport #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 18736b4e2ddSMike Rapoport #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 18836b4e2ddSMike Rapoport #define CONFIG_SYS_INIT_RAM_SIZE 0x800 18936b4e2ddSMike Rapoport #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 19036b4e2ddSMike Rapoport CONFIG_SYS_INIT_RAM_SIZE - \ 19136b4e2ddSMike Rapoport GENERATED_GBL_DATA_SIZE) 19236b4e2ddSMike Rapoport 1932b8754b2SIgor Grinberg /* Status LED */ 194ebc18afdSIgor Grinberg #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 1952b8754b2SIgor Grinberg 19660e6bdccSNikita Kiryanov #define CONFIG_SPLASHIMAGE_GUARD 19760e6bdccSNikita Kiryanov 1987878ca51SNikita Kiryanov /* Display Configuration */ 1997878ca51SNikita Kiryanov #define LCD_BPP LCD_COLOR16 2007878ca51SNikita Kiryanov 201f35034feSNikita Kiryanov #define CONFIG_SPLASH_SCREEN 202f82eb2faSNikita Kiryanov #define CONFIG_SPLASH_SOURCE 203f35034feSNikita Kiryanov #define CONFIG_BMP_16BPP 20463c4f17bSNikita Kiryanov #define CONFIG_SCF0403_LCD 20563c4f17bSNikita Kiryanov 2063e51b7c8SStefan Roese /* Defines for SPL */ 2073e51b7c8SStefan Roese 208e2ccdf89SPaul Kocialkowski #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 209205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 2103e51b7c8SStefan Roese 2113e51b7c8SStefan Roese #define CONFIG_SPL_NAND_BASE 2123e51b7c8SStefan Roese #define CONFIG_SPL_NAND_DRIVERS 2133e51b7c8SStefan Roese #define CONFIG_SPL_NAND_ECC 2143e51b7c8SStefan Roese 2153e51b7c8SStefan Roese /* NAND boot config */ 2163e51b7c8SStefan Roese #define CONFIG_SYS_NAND_5_ADDR_CYCLE 2173e51b7c8SStefan Roese #define CONFIG_SYS_NAND_PAGE_COUNT 64 2183e51b7c8SStefan Roese #define CONFIG_SYS_NAND_PAGE_SIZE 2048 2193e51b7c8SStefan Roese #define CONFIG_SYS_NAND_OOBSIZE 64 2203e51b7c8SStefan Roese #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 2213e51b7c8SStefan Roese #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 2223e51b7c8SStefan Roese /* 2233e51b7c8SStefan Roese * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 2243e51b7c8SStefan Roese * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 2253e51b7c8SStefan Roese */ 2263e51b7c8SStefan Roese #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 2273e51b7c8SStefan Roese 10, 11, 12 } 2283e51b7c8SStefan Roese #define CONFIG_SYS_NAND_ECCSIZE 512 2293e51b7c8SStefan Roese #define CONFIG_SYS_NAND_ECCBYTES 3 2303e51b7c8SStefan Roese #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 2313e51b7c8SStefan Roese 2323e51b7c8SStefan Roese #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 2333e51b7c8SStefan Roese #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 2343e51b7c8SStefan Roese 2353e51b7c8SStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40200800 236fa2f81b0STom Rini #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 237fa2f81b0STom Rini CONFIG_SPL_TEXT_BASE) 2383e51b7c8SStefan Roese 2393e51b7c8SStefan Roese /* 2403e51b7c8SStefan Roese * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 2413e51b7c8SStefan Roese * older x-loader implementations. And move the BSS area so that it 2423e51b7c8SStefan Roese * doesn't overlap with TEXT_BASE. 2433e51b7c8SStefan Roese */ 2443e51b7c8SStefan Roese #define CONFIG_SPL_BSS_START_ADDR 0x80100000 2453e51b7c8SStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 2463e51b7c8SStefan Roese 2473e51b7c8SStefan Roese #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 2483e51b7c8SStefan Roese #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 2493e51b7c8SStefan Roese 250bcb447e1SNikita Kiryanov /* EEPROM */ 251bcb447e1SNikita Kiryanov #define CONFIG_ENV_EEPROM_IS_ON_I2C 252bcb447e1SNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 253bcb447e1SNikita Kiryanov #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 254bcb447e1SNikita Kiryanov #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 255bcb447e1SNikita Kiryanov #define CONFIG_SYS_EEPROM_SIZE 256 256bcb447e1SNikita Kiryanov 25736b4e2ddSMike Rapoport #endif /* __CONFIG_H */ 258